diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2005-12-09 22:48:48 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2005-12-09 22:48:48 +0000 |
| commit | ab24ed2a322ec0c8be04ec684c75bc73faa1d346 (patch) | |
| tree | 2b03d010fa3f5672ae7a24b638d26546464a50b6 | |
| parent | b915f3110d74823e7b56d2c9cc4b83439bbedebc (diff) | |
Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24648 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 16 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 9 |
2 files changed, 22 insertions, 3 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index f19f148d1a..63cf7b2668 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -394,6 +394,22 @@ public: Ops.push_back(Op5); return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops); } + SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1, + MVT::ValueType VT2, SDOperand Op1, SDOperand Op2, + SDOperand Op3, SDOperand Op4, SDOperand Op5, + SDOperand Op6) { + std::vector<MVT::ValueType> ResultTys; + ResultTys.push_back(VT1); + ResultTys.push_back(VT2); + std::vector<SDOperand> Ops; + Ops.push_back(Op1); + Ops.push_back(Op2); + Ops.push_back(Op3); + Ops.push_back(Op4); + Ops.push_back(Op5); + Ops.push_back(Op6); + return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops); + } SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1, MVT::ValueType VT2, std::vector<SDOperand> &Ops) { std::vector<MVT::ValueType> ResultTys; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index a0f4d925c9..bba3cb2230 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1165,11 +1165,14 @@ def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), } // end isConvertibleToThreeAddress } // end isCommutable def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), - "add{b} {$src2, $dst|$dst, $src2}", []>; + "add{b} {$src2, $dst|$dst, $src2}", + [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>; def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize; + "add{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize; def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "add{l} {$src2, $dst|$dst, $src2}", []>; + "add{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>; def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), "add{b} {$src2, $dst|$dst, $src2}", |