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authorJohnny Chen <johnny.chen@apple.com>2011-05-18 20:32:41 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-05-18 20:32:41 +0000
commita96581f4f70fa305e4d0726f20b0ec687fca7b7c (patch)
tree48aa49e268bccc8c69298095d54b0450c1ed4b1d
parentd46ba26a6b513086ad575e5db0069b03d41fca13 (diff)
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h2
-rw-r--r--test/MC/Disassembler/ARM/thumb-tests.txt3
2 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index 8d39982f56..fbb16b936a 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -957,7 +957,7 @@ static bool DisassembleThumb1CondBr(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned Imm8 = getT1Imm8(insn);
MI.addOperand(MCOperand::CreateImm(
- Opcode == ARM::tBcc ? SignExtend32<9>(Imm8 << 1) + 4
+ Opcode == ARM::tBcc ? SignExtend32<9>(Imm8 << 1)
: (int)Imm8));
// Predicate operands by ARMBasicMCBuilder::TryPredicateAndSBitModifier().
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 774dbe4b42..895a5bb346 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -262,3 +262,6 @@
# CHECK: nop.w
0xaf 0xf3 0x00 0x80
+
+# CHECK: bne #24
+0x0c 0xd1