diff options
author | Chris Lattner <sabre@nondot.org> | 2005-01-11 04:40:19 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2005-01-11 04:40:19 +0000 |
commit | a95589be3fae3f13230e2aa96b46b4a63fb4a995 (patch) | |
tree | 2f28bf6849631b05b8626a0b706de0b9bb47bb9b | |
parent | 99f997d2c1f1c381998c560df7c3beead6f2b96f (diff) |
Teach the address selector to make 'reg+reg' addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19457 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelPattern.cpp | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index f2edb651ae..bd06077215 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -443,9 +443,18 @@ bool ISel::SelectAddress(SDOperand N, X86AddressMode &AM) { } } - if (AM.BaseType != X86AddressMode::RegBase || - AM.Base.Reg) + // Is the base register already occupied? + if (AM.BaseType != X86AddressMode::RegBase || AM.Base.Reg) { + // If so, check to see if the scale index register is set. + if (AM.IndexReg == 0) { + AM.IndexReg = SelectExpr(N); + AM.Scale = 1; + return false; + } + + // Otherwise, we cannot select it. return true; + } // Default, generate it as a register. AM.BaseType = X86AddressMode::RegBase; |