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authorKevin Enderby <enderby@apple.com>2012-12-14 23:04:25 +0000
committerKevin Enderby <enderby@apple.com>2012-12-14 23:04:25 +0000
commita827a47923700c16256036ca0bda8c0ff6108fdb (patch)
tree803f5867742dc1b3334802ebe66bd47df6158c62
parent07acee7a09c4895904f827bf56cf15f6bf8ef9f6 (diff)
Make sure the alternate PC+imm syntax of LDR instruction with a small
immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp7
-rw-r--r--test/MC/ARM/basic-thumb2-instructions.s4
2 files changed, 10 insertions, 1 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 4685b1d193..6b42239747 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5723,7 +5723,12 @@ processInstruction(MCInst &Inst,
}
// Aliases for alternate PC+imm syntax of LDR instructions.
case ARM::t2LDRpcrel:
- Inst.setOpcode(ARM::t2LDRpci);
+ // Select the narrow version if the immediate will fit.
+ if (Inst.getOperand(1).getImm() > 0 &&
+ Inst.getOperand(1).getImm() <= 0xff)
+ Inst.setOpcode(ARM::tLDRpci);
+ else
+ Inst.setOpcode(ARM::t2LDRpci);
return true;
case ARM::t2LDRBpcrel:
Inst.setOpcode(ARM::t2LDRBpci);
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 23d9f5977a..d495c91c0e 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -3509,3 +3509,7 @@ _func:
@ CHECK: ldrh.w r11, [pc, #-22] @ encoding: [0x3f,0xf8,0x16,0xb0]
@ CHECK: ldrsb.w r11, [pc, #-22] @ encoding: [0x1f,0xf9,0x16,0xb0]
@ CHECK: ldrsh.w r11, [pc, #-22] @ encoding: [0x3f,0xf9,0x16,0xb0]
+
+@ rdar://12596361
+ ldr r1, [pc, #12]
+@ CHECK: ldr.n r1, [pc, #12] @ encoding: [0x03,0x49]