diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-06 16:24:34 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-06 16:24:34 +0000 |
| commit | a5e82a5748763eba327176def083eec688eb4d6b (patch) | |
| tree | 28890008f615a55fdd539f04cd7ae28bd399ad4b | |
| parent | f8bd392dce26226249b99bc1fa8d112602da3e63 (diff) | |
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vget_lane.ll | 2 |
2 files changed, 7 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 8b4d701fc7..2ec5ad4ec0 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -718,6 +718,12 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, if (SrcRC == ARM::DPR_8RegisterClass) SrcRC = ARM::DPR_VFP2RegisterClass; + // NEONMoveFixPass will convert VFP moves to NEON moves when profitable. + if (DestRC == ARM::DPR_VFP2RegisterClass) + DestRC = ARM::DPRRegisterClass; + if (SrcRC == ARM::DPR_VFP2RegisterClass) + SrcRC = ARM::DPRRegisterClass; + // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. if (DestRC == ARM::QPR_VFP2RegisterClass || DestRC == ARM::QPR_8RegisterClass) @@ -750,10 +756,6 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS); else if (DestRC == ARM::DPRRegisterClass) Opc = ARM::VMOVD; - else if (DestRC == ARM::DPR_VFP2RegisterClass || - SrcRC == ARM::DPR_VFP2RegisterClass) - // Always use neon reg-reg move if source or dest is NEON-only regclass. - Opc = ARM::VMOVDneon; else if (DestRC == ARM::QPRRegisterClass) Opc = ARM::VMOVQ; else if (DestRC == ARM::QQPRRegisterClass) diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index bc10da09bb..05e7f50909 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -205,7 +205,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind { ;CHECK: test_vset_lanef32: ;CHECK: vmov.f32 s3, s0 -;CHECK: vmov d0, d1 +;CHECK: vmov.f64 d0, d1 entry: %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1] ret <2 x float> %0 |