diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2009-10-07 22:57:01 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-10-07 22:57:01 +0000 |
| commit | a4288080e62c6ecf94ebeafe84ab33a3b627d209 (patch) | |
| tree | cb1cd54eb4b9d3f6df5d91a6823656b0f10fcc66 | |
| parent | 9f3a559dff691bc1ed85089cb0870cf30a4a2d96 (diff) | |
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/NEONPreAllocPass.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vld2.ll | 12 |
4 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 713cc2e73f..27b0ed20fd 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1357,6 +1357,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4i16: Opc = ARM::VLD2d16; break; case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD2d32; break; + case MVT::v1i64: Opc = ARM::VLD2d64; break; } SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 334f4965cb..11117cca3a 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -193,6 +193,9 @@ class VLD2Q<bits<4> op7_4, string OpcodeStr> def VLD2d8 : VLD2D<0b0000, "vld2.8">; def VLD2d16 : VLD2D<0b0100, "vld2.16">; def VLD2d32 : VLD2D<0b1000, "vld2.32">; +def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2), + (ins addrmode6:$addr), IIC_VLD1, + "vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>; def VLD2q8 : VLD2Q<0b0000, "vld2.8">; def VLD2q16 : VLD2Q<0b0100, "vld2.16">; diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp index 0c167a12c5..e795e1a755 100644 --- a/lib/Target/ARM/NEONPreAllocPass.cpp +++ b/lib/Target/ARM/NEONPreAllocPass.cpp @@ -49,6 +49,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs, case ARM::VLD2d8: case ARM::VLD2d16: case ARM::VLD2d32: + case ARM::VLD2d64: case ARM::VLD2LNd8: case ARM::VLD2LNd16: case ARM::VLD2LNd32: diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 4456f603b8..23f7d2ca0c 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -4,6 +4,7 @@ %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> } %struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> } %struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> } +%struct.__neon_int64x1x2_t = type { <1 x i64>, <1 x i64> } %struct.__neon_int8x16x2_t = type { <16 x i8>, <16 x i8> } %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } @@ -50,6 +51,16 @@ define <2 x float> @vld2f(float* %A) nounwind { ret <2 x float> %tmp4 } +define <1 x i64> @vld2i64(i64* %A) nounwind { +;CHECK: vld2i64: +;CHECK: vld1.64 + %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i64* %A) + %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1 + %tmp4 = add <1 x i64> %tmp2, %tmp3 + ret <1 x i64> %tmp4 +} + define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;CHECK: vld2Qi8: ;CHECK: vld2.8 @@ -94,6 +105,7 @@ declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8*) nounwind readonl declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8*) nounwind readonly declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8*) nounwind readonly declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8*) nounwind readonly +declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8*) nounwind readonly declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8*) nounwind readonly declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8*) nounwind readonly |