diff options
| author | Bill Wendling <isanbard@gmail.com> | 2011-03-15 20:47:26 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-03-15 20:47:26 +0000 |
| commit | a24cb40be24e854faa8fb2c2148422a19c4a0ea5 (patch) | |
| tree | c287e4f701e899faefab85f2f862e0e0340c196d | |
| parent | 4f9fc854bc8d1482e65cd8fad464644a24fca4bf (diff) | |
Some minor cleanups based on feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vext.ll | 12 |
3 files changed, 16 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 665c823316..180b2c3b63 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -854,8 +854,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::VTRN: return "ARMISD::VTRN"; case ARMISD::VTBL1: return "ARMISD::VTBL1"; case ARMISD::VTBL2: return "ARMISD::VTBL2"; - case ARMISD::VTBL3: return "ARMISD::VTBL3"; - case ARMISD::VTBL4: return "ARMISD::VTBL4"; case ARMISD::VMULLs: return "ARMISD::VMULLs"; case ARMISD::VMULLu: return "ARMISD::VMULLu"; case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; @@ -4076,10 +4074,10 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, &VTBLMask[0], 8)); - else - return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, - &VTBLMask[0], 8)); + + return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, + &VTBLMask[0], 8)); } static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 8eb4525b82..402e1c6c5d 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -155,8 +155,6 @@ namespace llvm { VTRN, // transpose VTBL1, // 1-register shuffle with mask VTBL2, // 2-register shuffle with mask - VTBL3, // 3-register shuffle with mask - VTBL4, // 4-register shuffle with mask // Vector multiply long: VMULLs, // ...signed diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index c8d9045219..49a042b7e1 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -121,3 +121,15 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> ret <4 x i16> %tmp2 } + +; The actual shuffle code only handles some cases, make sure we check +; this rather than blindly emitting a VECTOR_SHUFFLE (infinite +; lowering loop can result otherwise). +define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: test_illegal: +;CHECK: vst1.16 + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9> + ret <8 x i16> %tmp3 +} |