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| author | Duraid Madina <duraid@octopus.com.au> | 2005-11-04 09:59:06 +0000 |
|---|---|---|
| committer | Duraid Madina <duraid@octopus.com.au> | 2005-11-04 09:59:06 +0000 |
| commit | 9f7290633adeb1b81fca3f9ac841c8fd9cc32a02 (patch) | |
| tree | a8c1be836914e27139758cbcfd72ed97fb60c072 | |
| parent | 7d090f3485b5a17431b5a956fdd5d1fc03cbd5d5 (diff) | |
add support for loading bools
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24182 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/IA64/IA64ISelDAGToDAG.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 9b26a25e9a..129d381636 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -369,7 +369,13 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) { unsigned Opc; switch (TypeBeingLoaded) { default: N->dump(); assert(0 && "Cannot load this type!"); - // FIXME: bools? case MVT::i1: + case MVT::i1: { // this is a bool + Opc = IA64::LD1; // first we load a byte, then compare for != 0 + CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, + CurDAG->getTargetNode(Opc, MVT::i64, Address), + CurDAG->getRegister(IA64::r0, MVT::i64), Chain); + return SDOperand(N, Op.ResNo); // XXX: early exit + } case MVT::i8: Opc = IA64::LD1; break; case MVT::i16: Opc = IA64::LD2; break; case MVT::i32: Opc = IA64::LD4; break; |