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| author | David Greene <greened@obbligato.org> | 2011-01-31 20:39:01 +0000 |
|---|---|---|
| committer | David Greene <greened@obbligato.org> | 2011-01-31 20:39:01 +0000 |
| commit | 9f08f60993a3a51db317a87dd6e8040af81ed306 (patch) | |
| tree | 0b9eed54c2f4fcb212f06eda3809ab5cb3a364d6 | |
| parent | fd2ad8783cd215f56c7a4e1f1c4fe0ae879d4008 (diff) | |
Fix vector sign extend to put the source and destination types in the
correct places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124601 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 6e6874c140..25f6fd000b 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1167,10 +1167,10 @@ class XSHWRegInst<RegisterClass rclass>: [(set rclass:$rDest, (sext R16C:$rSrc))]>; multiclass ExtendHalfwordWord { - def v4i32: XSHWVecInst<v4i32, v8i16>; - + def v4i32: XSHWVecInst<v8i16, v4i32>; + def r16: XSHWRegInst<R32C>; - + def r32: XSHWInRegInst<R32C, [(set R32C:$rDest, (sext_inreg R32C:$rSrc, i16))]>; def r64: XSHWInRegInst<R64C, [/* no pattern */]>; |