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authorChris Lattner <sabre@nondot.org>2006-02-02 20:00:41 +0000
committerChris Lattner <sabre@nondot.org>2006-02-02 20:00:41 +0000
commit9c8dd970f773f7481b83c9368ad6324f2e17b444 (patch)
tree6e8525e48390a7ec6d4c062f183efd6cccf67dff
parent1d6ecd03ea1f9ce7db8650c5036d0fd47d404b4c (diff)
implement isStoreToStackSlot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25911 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp23
1 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 046d847fc9..1c0ec8b2cf 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -139,6 +139,29 @@ unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
return 0;
}
+unsigned X86RegisterInfo::isStoreToStackSlot(MachineInstr *MI,
+ int &FrameIndex) const {
+ switch (MI->getOpcode()) {
+ default: break;
+ case X86::MOV8mr:
+ case X86::MOV16mr:
+ case X86::MOV32mr:
+ case X86::FpSTP64m:
+ case X86::MOVSSmr:
+ case X86::MOVSDmr:
+ if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
+ MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
+ MI->getOperand(3).getImmedValue() == 1 &&
+ MI->getOperand(4).getReg() == 0 &&
+ MI->getOperand(5).getImmedValue() == 0) {
+ FrameIndex = MI->getOperand(1).getFrameIndex();
+ return MI->getOperand(4).getReg();
+ }
+ break;
+ }
+ return 0;
+}
+
static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {