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authorMisha Brukman <brukman+llvm@gmail.com>2002-12-12 23:19:51 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2002-12-12 23:19:51 +0000
commit9ada014ec09579a7dd3833f779a1de82bd71bce1 (patch)
treea98e41315c09b97fea17b397e9ae923e9d0790a9
parent9f32791fe717aeeaa0566975facb1336cfc5e9e8 (diff)
Define the 2-address flag used by X86 instructions (add,sub,and,or,xor) that
need to be declared as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4975 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/Target/MachineInstrInfo.h6
-rw-r--r--include/llvm/Target/TargetInstrInfo.h6
2 files changed, 10 insertions, 2 deletions
diff --git a/include/llvm/Target/MachineInstrInfo.h b/include/llvm/Target/MachineInstrInfo.h
index a453b4007c..f4a6a7714c 100644
--- a/include/llvm/Target/MachineInstrInfo.h
+++ b/include/llvm/Target/MachineInstrInfo.h
@@ -54,7 +54,8 @@ const unsigned M_PREFETCH_FLAG = 1 << 11;
const unsigned M_STORE_FLAG = 1 << 12;
const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
const unsigned M_PSEUDO_FLAG = 1 << 14;
-
+// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
+const unsigned M_2_ADDR_FLAG = 1 << 15;
struct MachineInstrDescriptor {
const char * Name; // Assembly language mnemonic for the opcode.
@@ -186,6 +187,9 @@ public:
bool isPseudoInstr(const MachineOpCode opCode) const {
return get(opCode).Flags & M_PSEUDO_FLAG;
}
+ bool isTwoAddrInstr(const MachineOpCode opCode) const {
+ return get(opCode).Flags & M_2_ADDR_FLAG;
+ }
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index a453b4007c..f4a6a7714c 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -54,7 +54,8 @@ const unsigned M_PREFETCH_FLAG = 1 << 11;
const unsigned M_STORE_FLAG = 1 << 12;
const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
const unsigned M_PSEUDO_FLAG = 1 << 14;
-
+// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
+const unsigned M_2_ADDR_FLAG = 1 << 15;
struct MachineInstrDescriptor {
const char * Name; // Assembly language mnemonic for the opcode.
@@ -186,6 +187,9 @@ public:
bool isPseudoInstr(const MachineOpCode opCode) const {
return get(opCode).Flags & M_PSEUDO_FLAG;
}
+ bool isTwoAddrInstr(const MachineOpCode opCode) const {
+ return get(opCode).Flags & M_2_ADDR_FLAG;
+ }
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued