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authorEvan Cheng <evan.cheng@apple.com>2008-11-20 02:25:51 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-11-20 02:25:51 +0000
commit97c573d5de4f729f9b3a5db59c6daa3a6fc7efe4 (patch)
treef5e0a11891a63bb63e887216a9bc918a4d7a67e1
parent40362067de30a493951e084ba59d9b4fb1654a20 (diff)
Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59696 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp4
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index b621c41e12..56fc55315f 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -686,9 +686,7 @@ unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
const TargetInstrDesc &TID) const {
- unsigned e = TID.getNumOperands();
- if (e) --e; // Looks at the last non-implicit operand as well.
- for (unsigned i = MI.getNumOperands(); i != e; --i) {
+ for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
const MachineOperand &MO = MI.getOperand(i-1);
if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
return 1 << ARMII::S_BitShift;