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author | Johnny Chen <johnny.chen@apple.com> | 2010-02-19 02:12:06 +0000 |
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committer | Johnny Chen <johnny.chen@apple.com> | 2010-02-19 02:12:06 +0000 |
commit | 8f5e04098fe14d4a0e4da67b93ed471ba863e3e9 (patch) | |
tree | 1793882e086450d326fbe4f4827d277b48fbe93a | |
parent | efd9e9505167a398ba3c4924b09a47bd4d688e51 (diff) |
Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.
DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
asr r0, r0, #1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96654 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index da94e093a5..59495409e6 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1278,6 +1278,30 @@ def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi, "mov", "\t$dst, $src, rrx", [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; +//===----------------------------------------------------------------------===// +// Shift Instructions. +// +// These are for disassembly only. See also MOVs above. + +class AShI<string opc, bits<2> type> + : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src, am3offset:$offset), LdMiscFrm, + IIC_iMOVsr, opc, "\t$dst, $src, $offset", []>, UnaryDP { + let Inst{6-5} = type; + let Inst{25} = 0; +} + +def LSL : AShI<"lsl", 0b00>; +def LSR : AShI<"lsr", 0b01>; +def ASR : AShI<"asr", 0b10>; +def ROR : AShI<"ror", 0b11>; + +def RRX : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), LdMiscFrm, IIC_iMOVsr, + "rrx", "\t$dst, $src", []>, UnaryDP { + let Inst{25} = 0; + let Inst{11-7} = 0b00000; + let Inst{6-4} = 0b110; +} + // These aren't really mov instructions, but we have to define them this way // due to flag operands. |