diff options
author | Eric Christopher <echristo@apple.com> | 2011-04-12 23:23:14 +0000 |
---|---|---|
committer | Eric Christopher <echristo@apple.com> | 2011-04-12 23:23:14 +0000 |
commit | 8e98de9979fa08dac650bc6ae884e809da2cfdaa (patch) | |
tree | 79ea3361300dcdb65501bd11536dd2e5784a46b0 | |
parent | 161b2f45c2413a9aa3bb3003d043f58c21dfd319 (diff) |
Fix a bug where we were counting the alias sets as completely used
registers for fast allocation.
Fixes rdar://9207598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129408 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/RegAllocFast.cpp | 2 | ||||
-rw-r--r-- | test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll | 15 |
2 files changed, 15 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 7bb849ef54..30ecea0018 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -442,8 +442,6 @@ unsigned RAFast::calcSpillCost(unsigned PhysReg) const { unsigned Cost = 0; for (const unsigned *AS = TRI->getAliasSet(PhysReg); unsigned Alias = *AS; ++AS) { - if (UsedInInstr.test(Alias)) - return spillImpossible; switch (unsigned VirtReg = PhysRegState[Alias]) { case regDisabled: break; diff --git a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll new file mode 100644 index 0000000000..eb23de0b97 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast +; Previously we'd crash as out of registers on this input by clobbering all of +; the aliases. +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +define void @_Z8TestCasev() nounwind ssp { +entry: + %a = alloca float, align 4 + %tmp = load float* %a, align 4 + call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 + ret void +} + +!0 = metadata !{i32 109} |