Stop using isTwoAddress, switching to operand constraints instead.

Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31770 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 54 insertions, 38 deletions

diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 0e3fa905bf..e5578a80f7 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -246,11 +246,12 @@ def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
                      [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
 
 
-let isTwoAddress = 1, isCommutable = 1 in {
+let isCommutable = 1 in {
 def RLDIMI : MDForm_1<30, 3,
                       (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
                       "rldimi $rA, $rS, $SH, $MB", IntRotateD,
-                      []>, isPPC64;
+                      []>, isPPC64, RegConstraint<"$rSi = $rA">,
+                      NoEncode<"$rSi">;
 }
 
 // Rotate instructions.
@@ -290,10 +291,11 @@ def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
                    PPC970_DGroup_Cracked;
 
 // Update forms.
-def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
+def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp,
                             ptr_rc:$rA),
                     "lhau $rD, $disp($rA)", LdStGeneral,
-                    []>, RegConstraint<"$rA = $rA_result">;
+                    []>, RegConstraint<"$rA = $ea_result">,
+                    NoEncode<"$ea_result">;
 // NO LWAU!
 
 }
@@ -324,14 +326,16 @@ def LWZX8 : XForm_1<31,  23, (ops G8RC:$rD, memrr:$src),
 // Update forms.
 def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
                     "lbzu $rD, $addr", LdStGeneral,
-                    []>, RegConstraint<"$addr.reg = $ea_result">;
+                    []>, RegConstraint<"$addr.reg = $ea_result">,
+                    NoEncode<"$ea_result">;
 def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
                     "lhzu $rD, $addr", LdStGeneral,
-                    []>, RegConstraint<"$addr.reg = $ea_result">;
+                    []>, RegConstraint<"$addr.reg = $ea_result">,
+                    NoEncode<"$ea_result">;
 def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
                     "lwzu $rD, $addr", LdStGeneral,
-                    []>, RegConstraint<"$addr.reg = $ea_result">;
-
+                    []>, RegConstraint<"$addr.reg = $ea_result">,
+                    NoEncode<"$ea_result">;
 }
 
 
@@ -346,7 +350,8 @@ def LDX  : XForm_1<31,  21, (ops G8RC:$rD, memrr:$src),
                    
 def LDU  : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
                     "ldu $rD, $addr", LdStLD,
-                    []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64;
+                    []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
+                    NoEncode<"$ea_result">;
 
 }
 
@@ -378,13 +383,13 @@ def STDX_32  : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
 
 
 // Truncating stores.                       
-def STB8 : DForm_3<38, (ops G8RC:$rS, memri:$src),
+def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src),
                    "stb $rS, $src", LdStGeneral,
                    [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
-def STH8 : DForm_3<44, (ops G8RC:$rS, memri:$src),
+def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src),
                    "sth $rS, $src", LdStGeneral,
                    [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
-def STW8 : DForm_3<36, (ops G8RC:$rS, memri:$src),
+def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src),
                    "stw $rS, $src", LdStGeneral,
                    [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
 def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index ab02558e0e..ce86d8f358 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -120,11 +120,6 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
   let Inst{16-31} = B;
 }
 
-// Currently we make the use/def reg distinction in ISel, not tablegen
-class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
-              list<dag> pattern>
-  : DForm_1<opcode, OL, asmstr, itin, pattern>;
-
 class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
               list<dag> pattern>
   : I<opcode, OL, asmstr, itin> {
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 480d587cfc..0cf2bbc65e 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -200,6 +200,9 @@ class isDOT   {
 class RegConstraint<string C> {
   string Constraints = C;
 }
+class NoEncode<string E> {
+  string DisableEncoding = E;
+}
 
 
 //===----------------------------------------------------------------------===//
@@ -438,26 +441,33 @@ def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
 // Unindexed (r+i) Loads with Update (preinc).
 def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
                    "lbzu $rD, $addr", LdStGeneral,
-                   []>, RegConstraint<"$addr.reg = $ea_result">;
+                   []>, RegConstraint<"$addr.reg = $ea_result">,
+                   NoEncode<"$ea_result">;
 
 def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
                    "lhau $rD, $addr", LdStGeneral,
-                   []>, RegConstraint<"$addr.reg = $ea_result">;
+                   []>, RegConstraint<"$addr.reg = $ea_result">,
+                   NoEncode<"$ea_result">;
 
 def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
                    "lhzu $rD, $addr", LdStGeneral,
-                   []>, RegConstraint<"$addr.reg = $ea_result">;
+                   []>, RegConstraint<"$addr.reg = $ea_result">,
+                   NoEncode<"$ea_result">;
 
 def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
                    "lwzu $rD, $addr", LdStGeneral,
-                   []>, RegConstraint<"$addr.reg = $ea_result">;
+                   []>, RegConstraint<"$addr.reg = $ea_result">,
+                   NoEncode<"$ea_result">;
 
 def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
                   "lfs $rD, $addr", LdStLFDU,
-                  []>, RegConstraint<"$addr.reg = $ea_result">;
+                  []>, RegConstraint<"$addr.reg = $ea_result">,
+                   NoEncode<"$ea_result">;
+
 def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
                   "lfd $rD, $addr", LdStLFD,
-                  []>, RegConstraint<"$addr.reg = $ea_result">;
+                  []>, RegConstraint<"$addr.reg = $ea_result">,
+                   NoEncode<"$ea_result">;
 }
 
 // Indexed (r+r) Loads.
@@ -499,13 +509,13 @@ def LFDX   : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
 
 // Unindexed (r+i) Stores.
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-def STB  : DForm_3<38, (ops GPRC:$rS, memri:$src),
+def STB  : DForm_1<38, (ops GPRC:$rS, memri:$src),
                    "stb $rS, $src", LdStGeneral,
                    [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
-def STH  : DForm_3<44, (ops GPRC:$rS, memri:$src),
+def STH  : DForm_1<44, (ops GPRC:$rS, memri:$src),
                    "sth $rS, $src", LdStGeneral,
                    [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
-def STW  : DForm_3<36, (ops GPRC:$rS, memri:$src),
+def STW  : DForm_1<36, (ops GPRC:$rS, memri:$src),
                    "stw $rS, $src", LdStGeneral,
                    [(store GPRC:$rS, iaddr:$src)]>;
 def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
@@ -518,28 +528,33 @@ def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
 
 // Unindexed (r+i) Stores with Update (preinc).
 let isStore = 1, PPC970_Unit = 2 in {
-def STBU  : DForm_3<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
+def STBU  : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
                     "stbu $rS, $addr", LdStGeneral,
                     [/*(set ptr_rc:$ea_res,
                           (pre_truncsti8 GPRC:$rS, iaddr:$addr))*/]>,
-                    RegConstraint<"$addr.reg = $ea_res">;
-def STHU  : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
+                    RegConstraint<"$addr.reg = $ea_res">,
+                    NoEncode<"$ea_res">;
+def STHU  : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
                     "sthu $rS, $addr", LdStGeneral,
                     [/*(set ptr_rc:$ea_res,
                           (pre_truncsti16 GPRC:$rS, iaddr:$addr))*/]>,
-                    RegConstraint<"$addr.reg = $ea_res">;
-def STWU  : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
+                    RegConstraint<"$addr.reg = $ea_res">,
+                    NoEncode<"$ea_res">;
+def STWU  : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
                     "stwu $rS, $addr", LdStGeneral,
                     [/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS, iaddr:$addr))*/]>,
-                    RegConstraint<"$addr.reg = $ea_res">;
-def STFSU : DForm_3<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
+                    RegConstraint<"$addr.reg = $ea_res">,
+                    NoEncode<"$ea_res">;
+def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
                     "stfsu $rS, $addr", LdStGeneral,
                     [/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS, iaddr:$addr))*/]>,
-                    RegConstraint<"$addr.reg = $ea_res">;
-def STFDU : DForm_3<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
+                    RegConstraint<"$addr.reg = $ea_res">,
+                    NoEncode<"$ea_res">;
+def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
                     "stfdu $rS, $addr", LdStGeneral,
                     [/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS, iaddr:$addr))*/]>,
-                    RegConstraint<"$addr.reg = $ea_res">;
+                    RegConstraint<"$addr.reg = $ea_res">,
+                    NoEncode<"$ea_res">;
 }
 
 
@@ -965,12 +980,13 @@ def FSUBS : AForm_2<59, 20,
 let PPC970_Unit = 1 in {  // FXU Operations.
 // M-Form instructions.  rotate and mask instructions.
 //
-let isTwoAddress = 1, isCommutable = 1 in {
+let isCommutable = 1 in {
 // RLWIMI can be commuted if the rotate amount is zero.
 def RLWIMI : MForm_2<20,
                      (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 
                       u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
-                      []>, PPC970_DGroup_Cracked;
+                      []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
+                      NoEncode<"$rSi">;
 }
 def RLWINM : MForm_2<21,
                      (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),