diff options
| author | Daniel Dunbar <daniel@zuster.org> | 2009-05-18 16:43:04 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2009-05-18 16:43:04 +0000 |
| commit | 8c562e2d25d319f8bde7a1a60142203f316a2883 (patch) | |
| tree | 139bda2a4914e0e722a127c7e885836242e93cdf | |
| parent | 10978bd5918689334d44cd30e5cfe06588b6014d (diff) | |
Silence Release-Asserts warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72011 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Analysis/ScalarEvolution.cpp | 1 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp | 4 |
3 files changed, 11 insertions, 6 deletions
diff --git a/lib/Analysis/ScalarEvolution.cpp b/lib/Analysis/ScalarEvolution.cpp index 3ecb30232c..eaa847aa10 100644 --- a/lib/Analysis/ScalarEvolution.cpp +++ b/lib/Analysis/ScalarEvolution.cpp @@ -3081,6 +3081,7 @@ SCEVHandle ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) { } assert(0 && "Unknown SCEV type!"); + return 0; } /// getSCEVAtScope - This is a convenience function which does diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8a1dc5d937..6e0cc9f60a 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6000,9 +6000,9 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, // Get alias information for node. SDValue Ptr; - int64_t Size; - const Value *SrcValue; - int SrcValueOffset; + int64_t Size = 0; + const Value *SrcValue = 0; + int SrcValueOffset = 0; bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); // Starting off. @@ -6028,9 +6028,9 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, case ISD::STORE: { // Get alias information for Chain. SDValue OpPtr; - int64_t OpSize; - const Value *OpSrcValue; - int OpSrcValueOffset; + int64_t OpSize = 0; + const Value *OpSrcValue = 0; + int OpSrcValueOffset = 0; bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, OpSrcValue, OpSrcValueOffset); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index f1da2583f3..fb5e207e81 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -119,6 +119,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo, DstRC, SrcRC); assert(Emitted && "Unable to issue a copy instruction!\n"); + (void) Emitted; } SDValue Op(Node, ResNo); @@ -254,6 +255,7 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op, bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg, DstRC, SrcRC); assert(Emitted && "Unable to issue a copy instruction!\n"); + (void) Emitted; VReg = NewVReg; } } @@ -445,6 +447,7 @@ ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node, DstRC, SrcRC); assert(Emitted && "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); + (void) Emitted; SDValue Op(Node, 0); bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; @@ -568,6 +571,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg, DstTRC, SrcTRC); assert(Emitted && "Unable to issue a copy instruction!\n"); + (void) Emitted; break; } case ISD::CopyFromReg: { |