diff options
author | Wesley Peck <peckw@wesleypeck.com> | 2010-12-16 19:41:31 +0000 |
---|---|---|
committer | Wesley Peck <peckw@wesleypeck.com> | 2010-12-16 19:41:31 +0000 |
commit | 8a28f2137978d141402883815a3550b02ea5b1c8 (patch) | |
tree | 1ed74c0d219dcb240525ab1c8490e9a4d8253274 | |
parent | 3efad8fad41f6ba8141befcc3fc6662246b663ad (diff) |
Fix MBlaze backend call instructions so that arguments passed through registers
are correctly marked as used. This removes a hack where the call instructions
marked all possible argument registers as used in the tablegen description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121994 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp | 3 | ||||
-rw-r--r-- | lib/Target/MBlaze/MBlazeInstrInfo.td | 18 |
2 files changed, 11 insertions, 10 deletions
diff --git a/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp b/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp index 1073532c30..3f1b7b5352 100644 --- a/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp +++ b/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp @@ -146,7 +146,8 @@ static bool delayHasHazard(MachineBasicBlock::iterator &candidate, unsigned aop_reg = a->getOperand(aop).getReg(); for (unsigned bop = 0, bend = b->getNumOperands(); bop<bend; ++bop) { - if (b->getOperand(bop).isReg() && (!b->getOperand(bop).isImplicit())) { + if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit() && + !b->getOperand(bop).isKill()) { unsigned bop_reg = b->getOperand(bop).getReg(); if (aop_reg == bop_reg) return true; diff --git a/lib/Target/MBlaze/MBlazeInstrInfo.td b/lib/Target/MBlaze/MBlazeInstrInfo.td index 39ddd6ad35..0979091ad9 100644 --- a/lib/Target/MBlaze/MBlazeInstrInfo.td +++ b/lib/Target/MBlaze/MBlazeInstrInfo.td @@ -19,7 +19,7 @@ include "MBlazeInstrFormats.td" // def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>; def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_MBlazeIRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; -def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_MBlazeJmpLink : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; @@ -33,7 +33,8 @@ def MBlazeIRet : SDNode<"MBlazeISD::IRet", SDT_MBlazeIRet, [SDNPHasChain, SDNPOptInFlag]>; def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink, - [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>; + [SDNPHasChain,SDNPOptInFlag,SDNPOutFlag, + SDNPVariadic]>; def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>; @@ -290,7 +291,7 @@ class BranchI<bits<6> op, bits<5> br, string instr_asm> : // Branch and Link Instructions //===----------------------------------------------------------------------===// class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : - TA<op, flags, (outs), (ins GPR:$link, GPR:$target), + TA<op, flags, (outs), (ins GPR:$link, GPR:$target, variable_ops), !strconcat(instr_asm, " $link, $target"), [], IIBranch> { let ra = br; @@ -298,7 +299,7 @@ class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : } class BranchLI<bits<6> op, bits<5> br, string instr_asm> : - TB<op, (outs), (ins GPR:$link, calltarget:$target), + TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops), !strconcat(instr_asm, " $link, $target"), [], IIBranch> { let ra = br; @@ -500,17 +501,16 @@ let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, def BGED : BranchC<0x27, 0x15, 0x000, "bged ">; } -let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1, +let isCall =1, hasDelaySlot = 1, Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12], - Uses = [R1,R5,R6,R7,R8,R9,R10] in { + Uses = [R1] in { def BRLID : BranchLI<0x2E, 0x14, "brlid ">; def BRALID : BranchLI<0x2E, 0x1C, "bralid ">; } -let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1, - isBarrier = 1, +let isCall = 1, hasDelaySlot = 1, Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12], - Uses = [R1,R5,R6,R7,R8,R9,R10] in { + Uses = [R1] in { def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">; def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">; } |