diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-19 19:28:37 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-19 19:28:37 +0000 |
| commit | 89dc8d790d1ab3c903dfdf211f651350438a72fe (patch) | |
| tree | 77edabfbaf6662bda4fffbf887e7a5e8111b424c | |
| parent | 9c39789c361d4fe2632f28fca74c9ea5fff3dafc (diff) | |
Remove the restriction on the first operand of the add node in SelectAddr.
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/Mips/tls.ll | 2 |
2 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index b17239d939..4ac51e84ef 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -160,9 +160,7 @@ SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) { // Generate: // lui $2, %hi($CPI1_0) // lwc1 $f0, %lo($CPI1_0)($2) - if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi || - Addr.getOperand(0).getOpcode() == ISD::LOAD) && - Addr.getOperand(1).getOpcode() == MipsISD::Lo) { + if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) { SDValue LoVal = Addr.getOperand(1); if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) || isa<GlobalAddressSDNode>(LoVal.getOperand(0))) { diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 3fa852b454..8f97793c18 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -55,7 +55,7 @@ entry: ; PIC: jalr $25 ; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i) ; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2 -; PIC: addiu ${{[0-9]+}}, $[[R1]], %dtprel_lo(f3.i) +; PIC: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]]) %0 = load i32* @f3.i, align 4 %inc = add nsw i32 %0, 1 |