diff options
| author | Eric Christopher <echristo@apple.com> | 2011-07-01 00:14:47 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2011-07-01 00:14:47 +0000 |
| commit | 89bd71fc53fc95f2526e07ec338a8c998e9ead8d (patch) | |
| tree | 5e8f5ca83dcaed758d50081beb33742ea7e30efc | |
| parent | c3882164cbf794dbe21816a2946a31bc9e02a419 (diff) | |
Add support for the 'x' constraint.
Part of rdar://9307836 and rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/ARM/inlineasm3.ll | 10 |
2 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 7828447875..22cd78f80b 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -7483,6 +7483,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const { case 'l': return C_RegisterClass; case 'w': return C_RegisterClass; case 'h': return C_RegisterClass; + case 'x': return C_RegisterClass; } } else if (Constraint.size() == 2) { switch (Constraint[0]) { @@ -7555,6 +7556,14 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, if (VT.getSizeInBits() == 128) return RCPair(0U, ARM::QPRRegisterClass); break; + case 'x': + if (VT == MVT::f32) + return RCPair(0U, ARM::SPR_8RegisterClass); + if (VT.getSizeInBits() == 64) + return RCPair(0U, ARM::DPR_8RegisterClass); + if (VT.getSizeInBits() == 128) + return RCPair(0U, ARM::QPR_8RegisterClass); + break; } } if (StringRef("{cc}").equals_lower(Constraint)) diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index 58687b9692..f09deb39f8 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -58,3 +58,13 @@ entry: call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind ret i32 0 } + +; Radar 9307836 & 9119939 + +define float @t6(float %y) nounwind { +entry: +; CHECK: t6 +; CHECK: flds s15, s0 + %0 = tail call float asm "flds s15, $0", "=x"() nounwind + ret float %0 +} |