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authorJim Grosbach <grosbach@apple.com>2011-08-11 21:41:59 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-11 21:41:59 +0000
commit89958d50c38022b367ca3367e6694b7cdf3ac483 (patch)
tree0eb6e73608c75c6aa3d2056142117bc1e9f0928d
parent2ef8241ce7898d49f882e2124064ea953bf9f512 (diff)
Tidy up comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td3
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index ec91bc412b..fe7c60950e 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2122,9 +2122,8 @@ def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
} // hasExtraDefRegAllocReq = 1
} // mayLoad = 1, neverHasSideEffects = 1
-// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
+// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
let mayLoad = 1, neverHasSideEffects = 1 in {
-
def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, LdFrm, IIC_iLoad_ru,