diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-14 00:58:47 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-12-14 00:58:47 +0000 |
| commit | 885b3283eacb01bf281245ed0c19ae8ccca1fc8a (patch) | |
| tree | 11b5e4299844ede2d4109740a563972fb557bbc4 | |
| parent | aca0da6876346d6384bd7d913b3dc34bc4626377 (diff) | |
Remove unused vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121741 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 402898905e..943da11ad3 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -273,7 +273,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl<LiveInterval*> &SplitVRegs) { // Populate a list of physical register spill candidates. - SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands; + SmallVector<unsigned, 8> PhysRegSpillCands; // Check for an available register in this class. AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs); |