diff options
| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-24 11:27:53 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-04-24 11:27:53 +0000 |
| commit | 87ffdbcb7b93db35d8ff87dfb84d6ae623a5f49f (patch) | |
| tree | 031ea94a62b73318bbcf6ce7616cc5b2809da0bb | |
| parent | f4478f99dd63503bf0f0e763bc6d684e738bfe3d (diff) | |
AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e16367ab42..8a11b45f0e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5443,12 +5443,6 @@ static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, ISDNo = X86ISD::BLENDPD; OpTy = MVT::v4f64; break; - case MVT::v16i16: - if (!Subtarget->hasAVX2()) - return SDValue(); - ISDNo = X86ISD::BLENDPW; - OpTy = MVT::v16i16; - break; } assert(ISDNo && "Invalid Op Number"); |