diff options
| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2011-01-17 11:59:20 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2011-01-17 11:59:20 +0000 |
| commit | 8702e8be8df5f2ba12ecc89580d5e7453a1a39cd (patch) | |
| tree | 830ec6410ddd944041516952475d4bd73362a815 | |
| parent | 5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 (diff) | |
Don't crash SPU BE with memory accesses with big alignmnet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123620 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/stores.ll | 9 |
2 files changed, 13 insertions, 4 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 2002f09386..43dcfdca6b 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -560,7 +560,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { assert( LN->getAddressingMode() == ISD::UNINDEXED && "we should get only UNINDEXED adresses"); // clean aligned loads can be selected as-is - if (InVT.getSizeInBits() == 128 && alignment == 16) + if (InVT.getSizeInBits() == 128 && (alignment%16) == 0) return SDValue(); // Get pointerinfos to the memory chunk(s) that contain the data to load @@ -573,7 +573,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { SDValue basePtr = LN->getBasePtr(); SDValue rotate; - if (alignment == 16) { + if ((alignment%16) == 0) { ConstantSDNode *CN; // Special cases for a known aligned load to simplify the base pointer @@ -777,7 +777,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { assert( SN->getAddressingMode() == ISD::UNINDEXED && "we should get only UNINDEXED adresses"); // clean aligned loads can be selected as-is - if (StVT.getSizeInBits() == 128 && alignment == 16) + if (StVT.getSizeInBits() == 128 && (alignment%16) == 0) return SDValue(); SDValue alignLoadVec; @@ -785,7 +785,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { SDValue the_chain = SN->getChain(); SDValue insertEltOffs; - if (alignment == 16) { + if ((alignment%16) == 0) { ConstantSDNode *CN; // Special cases for a known aligned load to simplify the base pointer // and insertion byte: diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index efc915ca26..7e0bf06b4e 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -162,3 +162,12 @@ define void @store_misaligned( i32 %val, i32* %ptr) { store i32 %val, i32*%ptr, align 2 ret void } + +define void @store_v8( <8 x float> %val, <8 x float>* %ptr ) +{ +;CHECK: stq +;CHECK: stq +;CHECK: bi $lr + store <8 x float> %val, <8 x float>* %ptr + ret void +} |