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authorJim Grosbach <grosbach@apple.com>2010-11-17 23:33:14 +0000
committerJim Grosbach <grosbach@apple.com>2010-11-17 23:33:14 +0000
commit85eb54cf0cfb0f328669080c45cf8cc298aa2868 (patch)
tree0f09863b796712d00f8ab86776803b7efe4147cb
parent56a756821842678a96f2baa8c6a53bd28fc2b69e (diff)
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
it as such. Add some encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td26
2 files changed, 24 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 01ca22cfbc..14b0acc037 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -455,6 +455,14 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
llvm_unreachable("Unhandled instruction encoding format!");
break;
}
+ case ARMII::MiscFrm:
+ if (MI.getOpcode() == ARM::LEApcrelJT) {
+ // Materialize jumptable address.
+ emitLEApcrelJTInstruction(MI);
+ break;
+ }
+ llvm_unreachable("Unhandled instruction encoding!");
+ break;
case ARMII::Pseudo:
emitPseudoInstruction(MI);
break;
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index e4375169d7..1121c68447 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1168,21 +1168,27 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
-// FIXME: These are marked as pseudos, but they're really not(?). They're just
-// the ADR instruction. Is this the right way to handle that? They need
-// encoding information regardless.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
-def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
- Pseudo, IIC_iALUi,
- "adr$p\t$dst, #$label", []>;
+// FIXME: We want one cannonical LEApcrel instruction and to express one or
+// both of these as pseudo-instructions that get expanded to it.
+def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
+ MiscFrm, IIC_iALUi,
+ "adr$p\t$Rd, #$label", []>;
} // neverHasSideEffects
-def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
+def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
(ins i32imm:$label, nohash_imm:$id, pred:$p),
- Pseudo, IIC_iALUi,
- "adr$p\t$dst, #${label}_${id}", []> {
- let Inst{25} = 1;
+ MiscFrm, IIC_iALUi,
+ "adr$p\t$Rd, #${label}_${id}", []> {
+ bits<4> p;
+ bits<4> Rd;
+ let Inst{31-28} = p;
+ let Inst{27-25} = 0b001;
+ let Inst{20} = 0;
+ let Inst{19-16} = 0b1111;
+ let Inst{15-12} = Rd;
+ // FIXME: Add label encoding/fixup
}
//===----------------------------------------------------------------------===//