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| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2002-04-01 20:28:48 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2002-04-01 20:28:48 +0000 |
| commit | 85e1e9c22f6b8f9bac4924e0692ab199bd69ba89 (patch) | |
| tree | 642084206c54af82c18bb648fa7209659cd7f675 | |
| parent | 69cd2b1adeac3ecec6435a4e1735f8a2daf25016 (diff) | |
Case numbers were not updated when Sparc.burg.in was changed
to add separate label for bitwise NOT operator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2091 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/SparcV9/SparcV9InstrSelection.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index 94b1ebcc5a..18b4a0a427 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -1327,6 +1327,7 @@ ThisIsAChainRule(int eruleno) case 242: case 243: case 244: + case 321: return true; break; default: @@ -1578,7 +1579,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, break; case 21: // bool: Not(bool): Both these are implemented as: - case 321: // reg: BNot(reg) : reg = reg XOR-NOT 0 + case 421: // reg: BNot(reg) : reg = reg XOR-NOT 0 M = new MachineInstr(XNOR); M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, subtreeRoot->leftChild()->getValue()); |