Use normal lvx for scalar_to_vector instead of lve*x. They do the exact

same thing and we have a dag node for the former.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27205 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 5 insertions, 20 deletions

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index b6709ac132..46cf60e998 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -222,7 +222,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::STFIWX:        return "PPCISD::STFIWX";
   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
-  case PPCISD::LVE_X:         return "PPCISD::LVE_X";
   case PPCISD::VPERM:         return "PPCISD::VPERM";
   case PPCISD::Hi:            return "PPCISD::Hi";
   case PPCISD::Lo:            return "PPCISD::Lo";
@@ -697,9 +696,8 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     // Store the input value into Value#0 of the stack slot.
     SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
                                   Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
-    // LVE_X it out.
-    return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, 
-                       DAG.getSrcValue(NULL));
+    // Load it out.
+    return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
   }
   case ISD::BUILD_VECTOR:
     // If this is a case we can't handle, return null and let the default
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index cad4ea84d9..7a7c6290ca 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -48,14 +48,6 @@ namespace llvm {
       // three v4f32 operands and producing a v4f32 result.
       VMADDFP, VNMSUBFP,
       
-      /// LVE_X - The PPC LVE*X instructions.  The size of the element loaded is
-      /// the size of the element type of the vector result.  The element loaded
-      /// depends on the alignment of the input pointer.
-      ///
-      /// The first operand is a token chain, the second is the address to load
-      /// the third is the SRCVALUE node.
-      LVE_X,
-      
       /// VPERM - The PPC VPERM Instruction.
       ///
       VPERM,
diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index 358c4b26f1..a215bbb4da 100644
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -69,13 +69,13 @@ def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
 let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
 def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
                    "lvebx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
+                   []>;
 def LVEHX: XForm_1<31,  39, (ops VRRC:$vD, memrr:$src),
                    "lvehx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
+                   []>;
 def LVEWX: XForm_1<31,  71, (ops VRRC:$vD, memrr:$src),
                    "lvewx $vD, $src", LdStGeneral,
-                   [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
+                   []>;
 def LVX  : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
                    "lvx $vD, $src", LdStGeneral,
                    [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
@@ -511,7 +511,3 @@ def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
 def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
           (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
 
-def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
-          (v4i32 (LVEWX xoaddr:$src))>;
-
-
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 518d266bdd..cb0f94b12f 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -53,7 +53,6 @@ def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
 def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
 
-def PPClve_x    : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
 def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
 
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift