aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDan Gohman <gohman@apple.com>2008-09-19 23:42:04 +0000
committerDan Gohman <gohman@apple.com>2008-09-19 23:42:04 +0000
commit7e8ef60e3cff69cadc73187c0fc0df22caad3994 (patch)
tree67cc2947fd979da2729ea783ae24eff10f764ec7
parentfee2d6937cf56a2018a0707f9ed2c9c02870df2b (diff)
Fix a FastISel GlobalVariable CSE bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56376 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86FastISel.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 040eb0d4f7..309a3f3f79 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -379,8 +379,10 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
// Check to see if we've already materialized this
// value in a register in this block.
- if (unsigned Reg = LocalValueMap[V])
- return Reg;
+ if (unsigned Reg = LocalValueMap[V]) {
+ AM.Base.Reg = Reg;
+ return true;
+ }
// Issue load from stub if necessary.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;