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| author | Chris Lattner <sabre@nondot.org> | 2005-11-02 01:47:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-11-02 01:47:04 +0000 |
| commit | 7c22575e3292a80b42ec6189d618976a464f7406 (patch) | |
| tree | 9a43b7413e71b9d0ee92a751ec2de24ed2b89d69 | |
| parent | 2c122ceefe898fef04e86650409ec6a19a0ad19b (diff) | |
Fix a source of undefined behavior when dealing with 64-bit types. This
may fix PR652. Thanks to Andrew for tracking down the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24145 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 048737f13e..b4bd5aa0b4 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -384,7 +384,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::ZERO_EXTEND: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); - return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); + return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI); case ISD::AssertZext: SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. |