diff options
| author | Chris Lattner <sabre@nondot.org> | 2003-08-03 22:12:47 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-08-03 22:12:47 +0000 |
| commit | 7af9a38d0f895a72ef58f165662993974a3b7bad (patch) | |
| tree | 8b21919a9b075039dbeb8070ead65f2b91af46bb | |
| parent | 76bf868ff31ea6424bb4e8f774b0d76ef3f6cade (diff) | |
Specify custom name for registers to get the ()'s in the name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7547 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index ee491ee6ff..0af7ed3cee 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -35,10 +35,10 @@ set Namespace = "X86" in { def FP6 : Register; // Floating point stack registers - def ST0 : Register; def ST1 : Register; - def ST2 : Register; def ST3 : Register; - def ST4 : Register; def ST5 : Register; - def ST6 : Register; def ST7 : Register; + def ST0 : NamedReg<"ST(0)">; def ST1 : NamedReg<"ST(1)">; + def ST2 : NamedReg<"ST(2)">; def ST3 : NamedReg<"ST(3)">; + def ST4 : NamedReg<"ST(4)">; def ST5 : NamedReg<"ST(5)">; + def ST6 : NamedReg<"ST(6)">; def ST7 : NamedReg<"ST(7)">; // Flags, Segment registers, etc... |