diff options
author | Jim Grosbach <grosbach@apple.com> | 2010-09-02 00:02:26 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2010-09-02 00:02:26 +0000 |
commit | 7af3a345a9aa1772d723c7e2c3a059dfdfba028d (patch) | |
tree | 4745342c447cca6173fa669525803bac3ee62077 | |
parent | 352f23529c47486d35662de031403de9428c309b (diff) |
trivial cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 5f4902e10f..af24e9c75c 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -475,10 +475,8 @@ def tcGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R9, R12]> { const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); GPRClass::iterator I; - if (Subtarget.isThumb1Only()) { - I = THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned)); - return I; - } + if (Subtarget.isThumb1Only()) + return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned)); if (Subtarget.isTargetDarwin()) { if (Subtarget.isR9Reserved()) |