diff options
| author | Nate Begeman <natebegeman@mac.com> | 2005-11-29 22:42:50 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-11-29 22:42:50 +0000 |
| commit | 7ac8e6b6a85525e81a39d2a48c40b3b652583902 (patch) | |
| tree | cdbe915fadef2922efc2d81df3061374e612701b | |
| parent | f0701842f7569c4065d31710db29a01ec323fa8c (diff) | |
Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 12 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 14 |
2 files changed, 18 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index d7a3e87836..ef3cf1a7ab 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -361,7 +361,16 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, bits<10> SPR; let Inst{6-10} = RT; - let Inst{11-20} = SPR; + let Inst{11} = SPR{4}; + let Inst{12} = SPR{3}; + let Inst{13} = SPR{2}; + let Inst{14} = SPR{1}; + let Inst{15} = SPR{0}; + let Inst{16} = SPR{9}; + let Inst{17} = SPR{8}; + let Inst{18} = SPR{7}; + let Inst{19} = SPR{6}; + let Inst{20} = SPR{5}; let Inst{21-30} = xo; let Inst{31} = 0; } @@ -411,7 +420,6 @@ class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, let Inst{31} = 0; } - class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr, InstrItinClass itin> : XFXForm_1<opcode, xo, OL, asmstr, itin>; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 486de43e74..38f4ba830e 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -560,15 +560,17 @@ def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA), // Note that although LR should be listed as `8' and CTR as `9' in the SPR // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9 // which means the SPR value needs to be multiplied by a factor of 32. -def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>; -def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>; +def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>; +def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>; def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>; def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS), "mtcrf $FXM, $rS", BrMCRX>; -def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), - "mfcr $rT, $FXM", SprMFCR>; -def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>; -def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>; +def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM), + "mfcr $rT, $FXM", SprMFCR>; +def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>; +def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>; +def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS", + SprMTSPR>; // XS-Form instructions. Just 'sradi' // |