diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2009-06-19 06:56:26 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-19 06:56:26 +0000 |
| commit | 7a42b08be8836149ea4e3f95ddcc42e198561df3 (patch) | |
| tree | 9e609572d58cc752296c6bcc9b9455074cd208d8 | |
| parent | 2fb070bf5a34f3fae89beb8609c92abc1b1a2551 (diff) | |
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73759 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 38a2fb9b4d..345f172deb 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -296,7 +296,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) // Use branch latency information to determine if-conversion limits. const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData(); - unsigned Latency = InstrItins.getLatency(TII->get(ARM::BL).getSchedClass()); + unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass()); if (Latency > 1) { setIfCvtBlockSizeLimit(Latency-1); if (Latency > 2) |