Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 2333 insertions, 4 deletions

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index f6451704c1..a8bbc9ec52 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -547,6 +547,7 @@ class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
                                          (i32 (LoadOp addrmode6:$Rn)),
                                          imm:$lane))]> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVLD1LN";
 }
 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
              PatFrag LoadOp>
@@ -558,6 +559,7 @@ class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
                                          (i32 (LoadOp addrmode6oneL32:$Rn)),
                                          imm:$lane))]> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVLD1LN";
 }
 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
   let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
@@ -597,7 +599,9 @@ class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
           (ins addrmode6:$Rn, am6offset:$Rm,
            DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
           "\\{$Vd[$lane]\\}, $Rn$Rm",
-          "$src = $Vd, $Rn.addr = $wb", []>;
+          "$src = $Vd, $Rn.addr = $wb", []> {
+  let DecoderMethod = "DecodeVLD1LN";
+}
 
 def VLD1LNd8_UPD  : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
   let Inst{7-5} = lane{2-0};
@@ -624,6 +628,7 @@ class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
           "$src1 = $Vd, $src2 = $dst2", []> {
   let Rm = 0b1111;
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD2LN";
 }
 
 def VLD2LNd8  : VLD2LN<0b0001, {?,?,?,?}, "8"> {
@@ -659,6 +664,7 @@ class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
           "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
           "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD2LN";
 }
 
 def VLD2LNd8_UPD  : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
@@ -693,6 +699,7 @@ class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
           "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
           "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVLD3LN";
 }
 
 def VLD3LNd8  : VLD3LN<0b0010, {?,?,?,0}, "8"> {
@@ -729,7 +736,9 @@ class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
           IIC_VLD3lnu, "vld3", Dt,
           "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
           "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
-          []>;
+          []> {
+  let DecoderMethod = "DecodeVLD3LN";
+}
 
 def VLD3LNd8_UPD  : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
   let Inst{7-5} = lane{2-0};
@@ -765,6 +774,7 @@ class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
           "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
   let Rm = 0b1111;
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD4LN";
 }
 
 def VLD4LNd8  : VLD4LN<0b0011, {?,?,?,?}, "8"> {
@@ -805,6 +815,7 @@ class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
           []> {
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVLD4LN"  ;
 }
 
 def VLD4LNd8_UPD  : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
@@ -1424,6 +1435,7 @@ class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
           IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
           [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVST1LN";
 }
 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
              PatFrag StoreOp, SDNode ExtractOp>
@@ -1432,6 +1444,7 @@ class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
           IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
           [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVST1LN";
 }
 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
   : VSTQLNPseudo<IIC_VST1ln> {
@@ -1472,7 +1485,9 @@ class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
           "\\{$Vd[$lane]\\}, $Rn$Rm",
           "$Rn.addr = $wb",
           [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
-                                  addrmode6:$Rn, am6offset:$Rm))]>;
+                                  addrmode6:$Rn, am6offset:$Rm))]> {
+  let DecoderMethod = "DecodeVST1LN";
+}
 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
   : VSTQLNWBPseudo<IIC_VST1lnu> {
   let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
@@ -1508,6 +1523,7 @@ class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
           "", []> {
   let Rm = 0b1111;
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVST2LN";
 }
 
 def VST2LNd8  : VST2LN<0b0001, {?,?,?,?}, "8"> {
@@ -1545,6 +1561,7 @@ class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
           "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
           "$addr.addr = $wb", []> {
   let Inst{4}   = Rn{4};
+  let DecoderMethod = "DecodeVST2LN";
 }
 
 def VST2LNd8_UPD  : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
@@ -1578,6 +1595,7 @@ class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
            nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
           "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
   let Rm = 0b1111;
+  let DecoderMethod = "DecodeVST3LN";
 }
 
 def VST3LNd8  : VST3LN<0b0010, {?,?,?,0}, "8"> {
@@ -1612,7 +1630,9 @@ class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
            DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
           IIC_VST3lnu, "vst3", Dt,
           "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
-          "$Rn.addr = $wb", []>;
+          "$Rn.addr = $wb", []> {
+  let DecoderMethod = "DecodeVST3LN";
+}
 
 def VST3LNd8_UPD  : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
   let Inst{7-5} = lane{2-0};
@@ -1647,6 +1667,7 @@ class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
           "", []> {
   let Rm = 0b1111;
   let Inst{4} = Rn{4};
+  let DecoderMethod = "DecodeVST4LN";
 }
 
 def VST4LNd8  : VST4LN<0b0011, {?,?,?,?}, "8"> {
@@ -1685,6 +1706,7 @@ class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
   "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
           "$Rn.addr = $wb", []> {
   let Inst{4} = Rn{4};
+  let DecoderMethod = "DecodeVST4LN";
 }
 
 def VST4LNd8_UPD  : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 5cebabc65b..e7b555a22f 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -141,6 +141,22 @@ static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 
 
 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -2560,3 +2576,447 @@ static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
 
   return true;
 }
+
+static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 6, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 2) != 0)
+        align = 4;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 6, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 2) != 0)
+        align = 4;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+
+static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      index = fieldFromInstruction32(Insn, 5, 3);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 1:
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 1) != 0)
+        align = 8;
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      index = fieldFromInstruction32(Insn, 5, 3);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 2;
+      break;
+    case 1:
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 5, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 4, 1) != 0)
+        align = 8;
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+
+static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        return false; // UNDEFINED
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+
+static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 8;
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        align = 4 << fieldFromInstruction32(Insn, 4, 2);
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
+static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
+                         uint64_t Address, const void *Decoder) {
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
+  unsigned size = fieldFromInstruction32(Insn, 10, 2);
+
+  unsigned align = 0;
+  unsigned index = 0;
+  unsigned inc = 1;
+  switch (size) {
+    default:
+      return false;
+    case 0:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 4;
+      index = fieldFromInstruction32(Insn, 5, 3);
+      break;
+    case 1:
+      if (fieldFromInstruction32(Insn, 4, 1))
+        align = 8;
+      index = fieldFromInstruction32(Insn, 6, 2);
+      if (fieldFromInstruction32(Insn, 5, 1))
+        inc = 2;
+      break;
+    case 2:
+      if (fieldFromInstruction32(Insn, 4, 2))
+        align = 4 << fieldFromInstruction32(Insn, 4, 2);
+      index = fieldFromInstruction32(Insn, 7, 1);
+      if (fieldFromInstruction32(Insn, 6, 1))
+        inc = 2;
+      break;
+  }
+
+  if (Rm != 0xF) { // Writeback
+    if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
+      return false;
+  }
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(align));
+  if (Rm != 0xF && Rm != 0xD) {
+    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
+      return false;
+  }
+
+  if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
+  if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
+  Inst.addOperand(MCOperand::CreateImm(index));
+
+  return true;
+}
+
diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
new file mode 100644
index 0000000000..d9482d7006
--- /dev/null
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -0,0 +1,1847 @@
+# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble < %s | FileCheck %s
+
+0x20 0x03 0xf1 0xf3
+# CHECK: vabs.s8	d16, d16
+0x20 0x03 0xf5 0xf3
+# CHECK: vabs.s16	d16, d16
+0x20 0x03 0xf9 0xf3
+# CHECK: vabs.s32	d16, d16
+0x20 0x07 0xf9 0xf3
+# CHECK: vabs.f32	d16, d16
+0x60 0x03 0xf1 0xf3
+# CHECK: vabs.s8	q8, q8
+0x60 0x03 0xf5 0xf3
+# CHECK: vabs.s16	q8, q8
+0x60 0x03 0xf9 0xf3
+# CHECK: vabs.s32	q8, q8
+0x60 0x07 0xf9 0xf3
+# CHECK: vabs.f32	q8, q8
+
+0x20 0x07 0xf0 0xf3
+# CHECK: vqabs.s8	d16, d16
+0x20 0x07 0xf4 0xf3
+# CHECK: vqabs.s16	d16, d16
+0x20 0x07 0xf8 0xf3
+# CHECK: vqabs.s32	d16, d16
+0x60 0x07 0xf0 0xf3
+# CHECK: vqabs.s8	q8, q8
+0x60 0x07 0xf4 0xf3
+# CHECK: vqabs.s16	q8, q8
+0x60 0x07 0xf8 0xf3
+# CHECK: vqabs.s32	q8, q8
+
+0xa1 0x07 0x40 0xf2
+# CHECK: vabd.s8	d16, d16, d17
+0xa1 0x07 0x50 0xf2
+# CHECK: vabd.s16	d16, d16, d17
+0xa1 0x07 0x60 0xf2
+# CHECK: vabd.s32	d16, d16, d17
+0xa1 0x07 0x40 0xf3
+# CHECK: vabd.u8	d16, d16, d17
+0xa1 0x07 0x50 0xf3
+# CHECK: vabd.u16	d16, d16, d17
+  0xa1 0x07 0x60 0xf3
+# CHECK: vabd.u32	d16, d16, d17
+0xa1 0x0d 0x60 0xf3
+# CHECK: vabd.f32	d16, d16, d17
+0xe2 0x07 0x40 0xf2
+# CHECK: vabd.s8	q8, q8, q9
+0xe2 0x07 0x50 0xf2
+# CHECK: vabd.s16	q8, q8, q9
+0xe2 0x07 0x60 0xf2
+# CHECK: vabd.s32	q8, q8, q9
+0xe2 0x07 0x40 0xf3
+# CHECK: vabd.u8	q8, q8, q9
+0xe2 0x07 0x50 0xf3
+# CHECK: vabd.u16	q8, q8, q9
+0xe2 0x07 0x60 0xf3
+# CHECK: vabd.u32	q8, q8, q9
+0xe2 0x0d 0x60 0xf3
+# CHECK: vabd.f32	q8, q8, q9
+
+0xa1 0x07 0xc0 0xf2
+# CHECK: vabdl.s8	q8, d16, d17
+0xa1 0x07 0xd0 0xf2
+# CHECK: vabdl.s16	q8, d16, d17
+0xa1 0x07 0xe0 0xf2
+# CHECK: vabdl.s32	q8, d16, d17
+0xa1 0x07 0xc0 0xf3
+# CHECK: vabdl.u8	q8, d16, d17
+0xa1 0x07 0xd0 0xf3
+# CHECK: vabdl.u16	q8, d16, d17
+0xa1 0x07 0xe0 0xf3
+# CHECK: vabdl.u32	q8, d16, d17
+
+0xb1 0x07 0x42 0xf2
+# CHECK: vaba.s8	d16, d18, d17
+0xb1 0x07 0x52 0xf2
+# CHECK: vaba.s16	d16, d18, d17
+0xb1 0x07 0x62 0xf2
+# CHECK: vaba.s32	d16, d18, d17
+0xb1 0x07 0x42 0xf3
+# CHECK: vaba.u8	d16, d18, d17
+0xb1 0x07 0x52 0xf3
+# CHECK: vaba.u16	d16, d18, d17
+0xb1 0x07 0x62 0xf3
+# CHECK: vaba.u32	d16, d18, d17
+0xf4 0x27 0x40 0xf2
+# CHECK: vaba.s8	q9, q8, q10
+0xf4 0x27 0x50 0xf2
+# CHECK: vaba.s16	q9, q8, q10
+0xf4 0x27 0x60 0xf2
+# CHECK: vaba.s32	q9, q8, q10
+0xf4 0x27 0x40 0xf3
+# CHECK: vaba.u8	q9, q8, q10
+0xf4 0x27 0x50 0xf3
+# CHECK: vaba.u16	q9, q8, q10
+0xf4 0x27 0x60 0xf3
+# CHECK: vaba.u32	q9, q8, q10
+
+0xa2 0x05 0xc3 0xf2
+# CHECK: vabal.s8	q8, d19, d18
+0xa2 0x05 0xd3 0xf2
+# CHECK: vabal.s16	q8, d19, d18
+0xa2 0x05 0xe3 0xf2
+# CHECK: vabal.s32	q8, d19, d18
+0xa2 0x05 0xc3 0xf3
+# CHECK: vabal.u8	q8, d19, d18
+0xa2 0x05 0xd3 0xf3
+# CHECK: vabal.u16	q8, d19, d18
+0xa2 0x05 0xe3 0xf3
+# CHECK: vabal.u32	q8, d19, d18
+
+
+
+
+0xa0 0x08 0x41 0xf2
+# CHECK: vadd.i8	d16, d17, d16
+0xa0 0x08 0x51 0xf2
+# CHECK: vadd.i16	d16, d17, d16
+0xa0 0x08 0x71 0xf2
+# CHECK: vadd.i64	d16, d17, d16
+0xa0 0x08 0x61 0xf2
+# CHECK: vadd.i32	d16, d17, d16
+0xa1 0x0d 0x40 0xf2
+# CHECK: vadd.f32	d16, d16, d17
+0xe2 0x0d 0x40 0xf2
+# CHECK: vadd.f32	q8, q8, q9
+
+0xa0 0x00 0xc1 0xf2
+# CHECK: vaddl.s8	q8, d17, d16
+0xa0 0x00 0xd1 0xf2
+# CHECK: vaddl.s16	q8, d17, d16
+0xa0 0x00 0xe1 0xf2
+# CHECK: vaddl.s32	q8, d17, d16
+0xa0 0x00 0xc1 0xf3
+# CHECK: vaddl.u8	q8, d17, d16
+0xa0 0x00 0xd1 0xf3
+# CHECK: vaddl.u16	q8, d17, d16
+0xa0 0x00 0xe1 0xf3
+# CHECK: vaddl.u32	q8, d17, d16
+
+0xa2 0x01 0xc0 0xf2
+# CHECK: vaddw.s8	q8, q8, d18
+0xa2 0x01 0xd0 0xf2
+# CHECK: vaddw.s16	q8, q8, d18
+0xa2 0x01 0xe0 0xf2
+# CHECK: vaddw.s32	q8, q8, d18
+0xa2 0x01 0xc0 0xf3
+# CHECK: vaddw.u8	q8, q8, d18
+0xa2 0x01 0xd0 0xf3
+# CHECK: vaddw.u16	q8, q8, d18
+0xa2 0x01 0xe0 0xf3
+# CHECK: vaddw.u32	q8, q8, d18
+
+0xa1 0x00 0x40 0xf2
+# CHECK: vhadd.s8	d16, d16, d17
+0xa1 0x00 0x50 0xf2
+# CHECK: vhadd.s16	d16, d16, d17
+0xa1 0x00 0x60 0xf2
+# CHECK: vhadd.s32	d16, d16, d17
+0xa1 0x00 0x40 0xf3
+# CHECK: vhadd.u8	d16, d16, d17
+0xa1 0x00 0x50 0xf3
+# CHECK: vhadd.u16	d16, d16, d17
+0xa1 0x00 0x60 0xf3
+# CHECK: vhadd.u32	d16, d16, d17
+0xe2 0x00 0x40 0xf2
+# CHECK: vhadd.s8	q8, q8, q9
+0xe2 0x00 0x50 0xf2
+# CHECK: vhadd.s16	q8, q8, q9
+0xe2 0x00 0x60 0xf2
+# CHECK: vhadd.s32	q8, q8, q9
+  0xe2 0x00 0x40 0xf3
+# CHECK: vhadd.u8	q8, q8, q9
+0xe2 0x00 0x50 0xf3
+# CHECK: vhadd.u16	q8, q8, q9
+0xe2 0x00 0x60 0xf3
+# CHECK: vhadd.u32	q8, q8, q9
+
+0xa1 0x01 0x40 0xf2
+# CHECK: vrhadd.s8	d16, d16, d17
+0xa1 0x01 0x50 0xf2
+# CHECK: vrhadd.s16	d16, d16, d17
+0xa1 0x01 0x60 0xf2
+# CHECK: vrhadd.s32	d16, d16, d17
+0xa1 0x01 0x40 0xf3
+# CHECK: vrhadd.u8	d16, d16, d17
+0xa1 0x01 0x50 0xf3
+# CHECK: vrhadd.u16	d16, d16, d17
+0xa1 0x01 0x60 0xf3
+# CHECK: vrhadd.u32	d16, d16, d17
+0xe2 0x01 0x40 0xf2
+# CHECK: vrhadd.s8	q8, q8, q9
+0xe2 0x01 0x50 0xf2
+# CHECK: vrhadd.s16	q8, q8, q9
+0xe2 0x01 0x60 0xf2
+# CHECK: vrhadd.s32	q8, q8, q9
+0xe2 0x01 0x40 0xf3
+# CHECK: vrhadd.u8	q8, q8, q9
+0xe2 0x01 0x50 0xf3
+# CHECK: vrhadd.u16	q8, q8, q9
+0xe2 0x01 0x60 0xf3
+# CHECK: vrhadd.u32	q8, q8, q9
+
+0xb1 0x00 0x40 0xf2
+# CHECK: vqadd.s8	d16, d16, d17
+0xb1 0x00 0x50 0xf2
+# CHECK: vqadd.s16	d16, d16, d17
+0xb1 0x00 0x60 0xf2
+# CHECK: vqadd.s32	d16, d16, d17
+0xb1 0x00 0x70 0xf2
+# CHECK: vqadd.s64	d16, d16, d17
+0xb1 0x00 0x40 0xf3
+# CHECK: vqadd.u8	d16, d16, d17
+0xb1 0x00 0x50 0xf3
+# CHECK: vqadd.u16	d16, d16, d17
+0xb1 0x00 0x60 0xf3
+# CHECK: vqadd.u32	d16, d16, d17
+0xb1 0x00 0x70 0xf3
+# CHECK: vqadd.u64	d16, d16, d17
+0xf2 0x00 0x40 0xf2
+# CHECK: vqadd.s8	q8, q8, q9
+0xf2 0x00 0x50 0xf2
+# CHECK: vqadd.s16	q8, q8, q9
+0xf2 0x00 0x60 0xf2
+# CHECK: vqadd.s32	q8, q8, q9
+0xf2 0x00 0x70 0xf2
+# CHECK: vqadd.s64	q8, q8, q9
+0xf2 0x00 0x40 0xf3
+# CHECK: vqadd.u8	q8, q8, q9
+0xf2 0x00 0x50 0xf3
+# CHECK: vqadd.u16	q8, q8, q9
+0xf2 0x00 0x60 0xf3
+# CHECK: vqadd.u32	q8, q8, q9
+0xf2 0x00 0x70 0xf3
+# CHECK: vqadd.u64	q8, q8, q9
+
+0xa2 0x04 0xc0 0xf2
+# CHECK: vaddhn.i16	d16, q8, q9
+0xa2 0x04 0xd0 0xf2
+# CHECK: vaddhn.i32	d16, q8, q9
+0xa2 0x04 0xe0 0xf2
+# CHECK: vaddhn.i64	d16, q8, q9
+0xa2 0x04 0xc0 0xf3
+# CHECK: vraddhn.i16	d16, q8, q9
+0xa2 0x04 0xd0 0xf3
+# CHECK: vraddhn.i32	d16, q8, q9
+0xa2 0x04 0xe0 0xf3
+# CHECK: vraddhn.i64	d16, q8, q9
+
+
+0x20 0x05 0xf0 0xf3
+# CHECK: vcnt.8	d16, d16
+0x60 0x05 0xf0 0xf3
+# CHECK: vcnt.8	q8, q8
+0xa0 0x04 0xf0 0xf3
+# CHECK: vclz.i8	d16, d16
+0xa0 0x04 0xf4 0xf3
+# CHECK: vclz.i16	d16, d16
+0xa0 0x04 0xf8 0xf3
+# CHECK: vclz.i32	d16, d16
+0xe0 0x04 0xf0 0xf3
+# CHECK: vclz.i8	q8, q8
+0xe0 0x04 0xf4 0xf3
+# CHECK: vclz.i16	q8, q8
+0xe0 0x04 0xf8 0xf3
+# CHECK: vclz.i32	q8, q8
+0x20 0x04 0xf0 0xf3
+# CHECK: vcls.s8	d16, d16
+0x20 0x04 0xf4 0xf3
+# CHECK: vcls.s16	d16, d16
+0x20 0x04 0xf8 0xf3
+# CHECK: vcls.s32	d16, d16
+0x60 0x04 0xf0 0xf3
+# CHECK: vcls.s8	q8, q8
+0x60 0x04 0xf4 0xf3
+# CHECK: vcls.s16	q8, q8
+0x60 0x04 0xf8 0xf3
+# CHECK: vcls.s32	q8, q8
+
+
+
+
+0xb0 0x01 0x41 0xf2
+# CHECK: vand	d16, d17, d16
+0xf2 0x01 0x40 0xf2
+# CHECK: vand	q8, q8, q9
+
+0xb0 0x01 0x41 0xf3
+# CHECK: veor	d16, d17, d16
+0xf2 0x01 0x40 0xf3
+# CHECK: veor	q8, q8, q9
+
+0xb0 0x01 0x61 0xf2
+# CHECK: vorr	d16, d17, d16
+0xf2 0x01 0x60 0xf2
+# CHECK: vorr	q8, q8, q9
+0x11 0x07 0xc0 0xf2
+# CHECK: vorr.i32	d16, #0x1000000
+0x51 0x07 0xc0 0xf2
+# CHECK: vorr.i32	q8, #0x1000000
+0x50 0x01 0xc0 0xf2
+# CHECK: vorr.i32	q8, #0x0
+
+0xb0 0x01 0x51 0xf2
+# CHECK: vbic	d16, d17, d16
+0xf2 0x01 0x50 0xf2
+# CHECK: vbic	q8, q8, q9
+0x3f 0x07 0xc7 0xf3
+# CHECK: vbic.i32	d16, #0xFF000000
+0x7f 0x07 0xc7 0xf3
+# CHECK: vbic.i32	q8, #0xFF000000
+
+0xb0 0x01 0x71 0xf2
+# CHECK: vorn	d16, d17, d16
+0xf2 0x01 0x70 0xf2
+# CHECK: vorn	q8, q8, q9
+
+0xa0 0x05 0xf0 0xf3
+# CHECK: vmvn	d16, d16
+0xe0 0x05 0xf0 0xf3
+# CHECK: vmvn	q8, q8
+
+0xb0 0x21 0x51 0xf3
+# CHECK: vbsl	d18, d17, d16
+0xf2 0x01 0x54 0xf3
+# CHECK: vbsl	q8, q10, q9
+
+
+# CHECK: vceq.i8	d16, d16, d17
+# CHECK: vceq.i16	d16, d16, d17
+# CHECK: vceq.i32	d16, d16, d17
+# CHECK: vceq.f32	d16, d16, d17
+# CHECK: vceq.i8	q8, q8, q9
+# CHECK: vceq.i16	q8, q8, q9
+# CHECK: vceq.i32	q8, q8, q9
+# CHECK: vceq.f32	q8, q8, q9
+
+0xb1 0x08 0x40 0xf3
+0xb1 0x08 0x50 0xf3
+0xb1 0x08 0x60 0xf3
+0xa1 0x0e 0x40 0xf2
+0xf2 0x08 0x40 0xf3
+0xf2 0x08 0x50 0xf3
+0xf2 0x08 0x60 0xf3
+0xe2 0x0e 0x40 0xf2
+
+# CHECK: vcge.s8	d16, d16, d17
+# CHECK: vcge.s16	d16, d16, d17
+# CHECK: vcge.s32	d16, d16, d17
+# CHECK: vcge.u8	d16, d16, d17
+# CHECK: vcge.u16	d16, d16, d17
+# CHECK: vcge.u32	d16, d16, d17
+# CHECK: vcge.f32	d16, d16, d17
+# CHECK: vcge.s8	q8, q8, q9
+# CHECK: vcge.s16	q8, q8, q9
+# CHECK: vcge.s32	q8, q8, q9
+# CHECK: vcge.u8	q8, q8, q9
+# CHECK: vcge.u16	q8, q8, q9
+# CHECK: vcge.u32	q8, q8, q9
+# CHECK: vcge.f32	q8, q8, q9
+# CHECK: vacge.f32	d16, d16, d17
+# CHECK: vacge.f32	q8, q8, q9
+
+0xb1 0x03 0x40 0xf2
+0xb1 0x03 0x50 0xf2
+0xb1 0x03 0x60 0xf2
+0xb1 0x03 0x40 0xf3
+0xb1 0x03 0x50 0xf3
+0xb1 0x03 0x60 0xf3
+0xa1 0x0e 0x40 0xf3
+0xf2 0x03 0x40 0xf2
+0xf2 0x03 0x50 0xf2
+0xf2 0x03 0x60 0xf2
+0xf2 0x03 0x40 0xf3
+0xf2 0x03 0x50 0xf3
+0xf2 0x03 0x60 0xf3
+0xe2 0x0e 0x40 0xf3
+0xb1 0x0e 0x40 0xf3
+0xf2 0x0e 0x40 0xf3
+
+# CHECK: vcgt.s8	d16, d16, d17
+# CHECK: vcgt.s16	d16, d16, d17
+# CHECK: vcgt.s32	d16, d16, d17
+# CHECK: vcgt.u8	d16, d16, d17
+# CHECK: vcgt.u16	d16, d16, d17
+# CHECK: vcgt.u32	d16, d16, d17
+# CHECK: vcgt.f32	d16, d16, d17
+# CHECK: vcgt.s8	q8, q8, q9
+# CHECK: vcgt.s16	q8, q8, q9
+# CHECK: vcgt.s32	q8, q8, q9
+# CHECK: vcgt.u8	q8, q8, q9
+# CHECK: vcgt.u16	q8, q8, q9
+# CHECK: vcgt.u32	q8, q8, q9
+# CHECK: vcgt.f32	q8, q8, q9
+# CHECK: vacgt.f32	d16, d16, d17
+# CHECK: vacgt.f32	q8, q8, q9
+
+0xa1 0x03 0x40 0xf2
+0xa1 0x03 0x50 0xf2
+0xa1 0x03 0x60 0xf2
+0xa1 0x03 0x40 0xf3
+0xa1 0x03 0x50 0xf3
+0xa1 0x03 0x60 0xf3