diff options
| author | Chad Rosier <mcrosier@apple.com> | 2012-11-30 18:29:01 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-11-30 18:29:01 +0000 |
| commit | 75cbb00727329ad11d5900d70c9f5d05cb375e65 (patch) | |
| tree | 27783bda623a1e337ddb7e39d98b2767211e6479 | |
| parent | f432be0c62a01a681100f72415d5eb958cf43ab1 (diff) | |
test/CodeGen/PowerPC/vec_mul.ll: Fix register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169020 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/PowerPC/vec_mul.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll index df83bf1d1d..dadf0ebb77 100644 --- a/test/CodeGen/PowerPC/vec_mul.ll +++ b/test/CodeGen/PowerPC/vec_mul.ll @@ -41,6 +41,6 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) { ; all bits set and shifting it 31 bits to left, resulting a an vector of ; 4 x 0x80000000 (-0.0 as float). ; CHECK: test_float: -; CHECK: vspltisw [[ZNEG:[0-9]+]], -1 -; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]] +; CHECK: vspltisw [[ZNEG:v[0-9]+]], -1 +; CHECK: vslw {{v[0-9]+}}, [[ZNEG]], [[ZNEG]] ; CHECK: vmaddfp |