Move if-conversion after all passes that may use register scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 3 insertions, 9 deletions

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 57b644026d..fc03da1a8d 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -88,19 +88,14 @@ bool ARMTargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) {
   return false;
 }
 
-bool ARMTargetMachine::addPostRegAlloc(FunctionPassManager &PM, bool Fast) {
-  if (Fast || !EnableIfConversion || Subtarget.isThumb())
-    return false;
-
-  PM.add(createIfConverterPass());
-  return true;
-}
-
 bool ARMTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
   if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
     PM.add(createARMLoadStoreOptimizationPass());
   
+  if (!Fast && EnableIfConversion && !Subtarget.isThumb())
+    PM.add(createIfConverterPass());
+
   PM.add(createARMConstantIslandPass());
   return true;
 }
diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
index dcdd1285f5..a50275c675 100644
--- a/lib/Target/ARM/ARMTargetMachine.h
+++ b/lib/Target/ARM/ARMTargetMachine.h
@@ -53,7 +53,6 @@ public:
   
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
-  virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast);
   virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);
   virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast, 
                                   std::ostream &Out);