diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2011-09-22 03:01:42 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2011-09-22 03:01:42 +0000 |
| commit | 74f3501d15c05a92eeb7962da76e97cabc3c7557 (patch) | |
| tree | 7e699406145150ebe5fa9cd59f51b2a556cd8879 | |
| parent | 459cad2dfda4163f84e858e9a586670b3adb090e (diff) | |
X86: Don't form min/max nodes if the target is missing SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 36e254b1f5..996dd12d3e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -12568,7 +12568,8 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, // instructions match the semantics of the common C idiom x<y?x:y but not // x<=y?x:y, because of how they handle negative zero (which can be // ignored in unsafe-math mode). - if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && + if (Subtarget->hasXMM() && + Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) { ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); |