diff options
| author | Chris Lattner <sabre@nondot.org> | 2010-10-10 18:34:00 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-10-10 18:34:00 +0000 |
| commit | 749dc72bdcf214b1a3e2b4eee37e836a39e6bdea (patch) | |
| tree | 840171b60f96922294b5a6aac81af61dfca7067d | |
| parent | 7d2e7bef90785b174a350f3bc4b240256be9831c (diff) | |
fix the expansion of va_arg instruction on PPC to know the arg
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/varargs.ll | 22 |
2 files changed, 26 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 7300fd5d6e..618e5c1c4d 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -73,6 +73,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setUseUnderscoreSetJmp(true); setUseUnderscoreLongJmp(true); + // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all + // arguments are at least 4/8 bytes aligned. + setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); + // Set up the register classes. addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll new file mode 100644 index 0000000000..813ec22463 --- /dev/null +++ b/test/CodeGen/PowerPC/varargs.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=ppc32 | FileCheck -check-prefix=P32 %s +; RUN: llc < %s -march=ppc64 | FileCheck -check-prefix=P64 %s + +; PR8327 +define i8* @test1(i8** %foo) nounwind { + %A = va_arg i8** %foo, i8* + ret i8* %A +} + +; P32: test1: +; P32: lwz r4, 0(r3) +; P32: addi r5, r4, 4 +; P32: stw r5, 0(r3) +; P32: lwz r3, 0(r4) +; P32: blr + +; P64: test1: +; P64: ld r4, 0(r3) +; P64: addi r5, r4, 8 +; P64: std r5, 0(r3) +; P64: ld r3, 0(r4) +; P64: blr |