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authorChris Lattner <sabre@nondot.org>2006-07-12 16:59:49 +0000
committerChris Lattner <sabre@nondot.org>2006-07-12 16:59:49 +0000
commit6d3465793f45f4d40e24cabf1f5867cc6c0db90a (patch)
tree3ea81cf71a2be53473f4cc3dbdc1ff06a7f32505
parent08c3f7b7c2c17e2d4411b0c807e29fd16cb6d669 (diff)
Add information preventing several register class constraints from working.
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29118 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index d96be87efd..4ebe4caad0 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4140,7 +4140,15 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
X86TargetLowering::ConstraintType
X86TargetLowering::getConstraintType(char ConstraintLetter) const {
switch (ConstraintLetter) {
- case 'A': return C_RegisterClass;
+ case 'A':
+ case 'r':
+ case 'R':
+ case 'l':
+ case 'q':
+ case 'Q':
+ case 'x':
+ case 'Y':
+ return C_RegisterClass;
default: return TargetLowering::getConstraintType(ConstraintLetter);
}
}