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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 14:09:07 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-04-18 14:09:07 +0000 |
| commit | 6b9f97dd892b0d61d8a1f0ee4f837058f2ca4552 (patch) | |
| tree | 1c5eca66c338066cb7d977fa9331a6316a25f181 | |
| parent | fa1ebc6abe95b79b7f82030eea53586a8704eb7e (diff) | |
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 20 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt | 18 |
2 files changed, 33 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 7b0a3ac42a..807577e769 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4646,22 +4646,32 @@ def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; // // Move to ARM core register from Special Register -def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, +def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> { bits<4> Rd; let Inst{23-16} = 0b00001111; + let Unpredictable{19-17} = 0b111; + let Inst{15-12} = Rd; - let Inst{7-4} = 0b0000; + + let Inst{11-0} = 0b000000000000; + let Unpredictable{11-0} = 0b110100001111; } -def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>; +def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, Requires<[IsARM]>; -def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, +// The MRSsys instruction is the MRS instruction from the ARM ARM, +// section B9.3.9, with the R bit set to 1. +def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> { bits<4> Rd; let Inst{23-16} = 0b01001111; + let Unpredictable{19-16} = 0b1111; + let Inst{15-12} = Rd; - let Inst{7-4} = 0b0000; + + let Inst{11-0} = 0b000000000000; + let Unpredictable{11-0} = 0b110100001111; } // Move from ARM core register to Special Register diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt new file mode 100644 index 0000000000..3e472cdbfb --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -0,0 +1,18 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x0f 0x01 +0x00 0xf0 0x0f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x00 0xf0 0x4f 0x01 +0x00 0xf0 0x4f 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x01 0x01 +0x0f 0x0d 0x01 0x01 + +# CHECK: warning: potentially undefined +# CHECK: 0x0f 0x0d 0x40 0x01 +0x0f 0x0d 0x40 0x01 + |