Need to special case splat after all. Make the second operand of splat

vector_shuffle undef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27250 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 18 insertions, 15 deletions

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 2ac4955df5..8383f431eb 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2397,21 +2397,21 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     MVT::ValueType VT = Op.getValueType();
     unsigned NumElems = PermMask.getNumOperands();
 
-    if (X86::isUNPCKLMask(PermMask.Val) ||
-        X86::isUNPCKHMask(PermMask.Val))
-      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
-      return SDOperand();
-
-    // PSHUFD's 2nd vector must be undef.
-    if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)) {
+    // Splat && PSHUFD's 2nd vector must be undef.
+    if (X86::isSplatMask(PermMask.Val) ||
+        ((MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val)))) {
       if (V2.getOpcode() != ISD::UNDEF)
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
       return SDOperand();
     }
 
+    if (X86::isUNPCKLMask(PermMask.Val) ||
+        X86::isUNPCKHMask(PermMask.Val))
+      // Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
+      return SDOperand();
+
     if (NumElems == 2 ||
-        X86::isSplatMask(PermMask.Val) ||
         X86::isSHUFPMask(PermMask.Val)) {
       return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
     }
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 513c0057a3..da6effad35 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -58,9 +58,9 @@ def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
   return getI8Imm(X86::getShuffleSHUFImmediate(N));
 }]>;
 
-def v2f64_v2i64_splat_mask : PatLeaf<(build_vector), [{
+def SSE_splat_mask : PatLeaf<(build_vector), [{
   return X86::isSplatMask(N);
-}]>;
+}], SHUFFLE_get_shuf_imm>;
 
 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
   return X86::isMOVLHPSMask(N);
@@ -1375,13 +1375,16 @@ def : Pat<(v16i8 (X86zexts2vec R8:$src)),
           (MOVZD128rr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
 
 // Splat v2f64 / v2i64
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (v2f64 VR128:$src),
-           v2f64_v2i64_splat_mask:$sm),
-          (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (v2i64 VR128:$src),
-           v2f64_v2i64_splat_mask:$sm),
+def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
+          (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>,   Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
           (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
 
+// Splat v4f32
+def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
+          (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
+      Requires<[HasSSE1]>;
+
 // Shuffle v4i32 if others do not match
 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
            SHUFP_shuffle_mask:$sm),