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authorMisha Brukman <brukman+llvm@gmail.com>2002-12-02 21:10:35 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2002-12-02 21:10:35 +0000
commit6877dd3fb05bb7f8fabf907e520c7d3ae0fab341 (patch)
treeb3f7f23c3a2afdf73959a9978bb135e04ac4bd1c
parent9f729a30b2e0648209f864da9da8aaa6a4be5e38 (diff)
Fix order of operands on a store from reg to [reg+offset].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4857 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 9b7256f9e6..4ec2971070 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -31,8 +31,8 @@ X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock *MBB,
unsigned ImmOffset, unsigned dataSize)
const
{
- MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5).addReg(SrcReg),
- DestReg, ImmOffset);
+ MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5),
+ DestReg, ImmOffset).addReg(SrcReg);
return ++(MBB->insert(MBBI, MI));
}