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| author | Anshuman Dasgupta <adasgupt@codeaurora.org> | 2013-02-13 22:56:34 +0000 |
|---|---|---|
| committer | Anshuman Dasgupta <adasgupt@codeaurora.org> | 2013-02-13 22:56:34 +0000 |
| commit | 666e0d3bc4a28540c1aa73b24573af70d1d46aea (patch) | |
| tree | bd2c8698b2139f8ac50ae5f32a6878ad774fda38 | |
| parent | ff91f2ef47cd16adffaa16ee83c45f6c3933a415 (diff) | |
Hexagon: add support for predicate-GPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/predicate-copy.ll | 8 |
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 6801467b47..d30cddaca5 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -426,6 +426,18 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); return; } + if (Hexagon::PredRegsRegClass.contains(SrcReg) && + Hexagon::IntRegsRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg). + addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + if (Hexagon::IntRegsRegClass.contains(SrcReg) && + Hexagon::PredRegsRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg). + addReg(SrcReg, getKillRegState(KillSrc)); + return; + } llvm_unreachable("Unimplemented"); } diff --git a/test/CodeGen/Hexagon/predicate-copy.ll b/test/CodeGen/Hexagon/predicate-copy.ll new file mode 100644 index 0000000000..552b687941 --- /dev/null +++ b/test/CodeGen/Hexagon/predicate-copy.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s + +; CHECK: r{{[0-9]+}} = p{{[0-9]+}} +define i1 @foo() { +entry: + ret i1 false +} + |