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authorSandeep Patel <deeppatel1987@gmail.com>2009-09-02 08:44:58 +0000
committerSandeep Patel <deeppatel1987@gmail.com>2009-09-02 08:44:58 +0000
commit65c3c8f323198b99b88b109654194540cf9b3fa5 (patch)
treeeb867222ef634a613f0f8df64edac4e1b46eb638
parent25f1992cf56799d3d887e7578c66d63ecba108fb (diff)
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/CodeGen/CallingConvLower.h7
-rw-r--r--include/llvm/Function.h13
-rw-r--r--include/llvm/Instructions.h17
-rw-r--r--include/llvm/Support/CallSite.h5
-rw-r--r--include/llvm/Target/TargetLowering.h13
-rw-r--r--lib/AsmParser/LLParser.cpp23
-rw-r--r--lib/AsmParser/LLParser.h2
-rw-r--r--lib/Bitcode/Reader/BitcodeReader.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/CallingConvLower.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp5
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp10
-rw-r--r--lib/Target/ARM/ARMISelLowering.h10
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp8
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.h8
-rw-r--r--lib/Target/Blackfin/BlackfinISelLowering.cpp6
-rw-r--r--lib/Target/Blackfin/BlackfinISelLowering.h6
-rw-r--r--lib/Target/CBackend/CBackend.cpp2
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp6
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.h6
-rw-r--r--lib/Target/CppBackend/CPPBackend.cpp4
-rw-r--r--lib/Target/MSIL/MSILWriter.cpp6
-rw-r--r--lib/Target/MSIL/MSILWriter.h5
-rw-r--r--lib/Target/MSP430/MSP430ISelLowering.cpp12
-rw-r--r--lib/Target/MSP430/MSP430ISelLowering.h12
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp8
-rw-r--r--lib/Target/Mips/MipsISelLowering.h8
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.cpp6
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.h6
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp24
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.h20
-rw-r--r--lib/Target/Sparc/SparcISelLowering.cpp6
-rw-r--r--lib/Target/Sparc/SparcISelLowering.h6
-rw-r--r--lib/Target/SystemZ/SystemZISelLowering.cpp12
-rw-r--r--lib/Target/SystemZ/SystemZISelLowering.h12
-rw-r--r--lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp4
-rw-r--r--lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp4
-rw-r--r--lib/Target/X86/X86FastISel.cpp7
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp23
-rw-r--r--lib/Target/X86/X86ISelLowering.h18
-rw-r--r--lib/Target/XCore/XCoreISelLowering.cpp12
-rw-r--r--lib/Target/XCore/XCoreISelLowering.h12
-rw-r--r--lib/VMCore/Core.cpp7
-rw-r--r--lib/VMCore/Instructions.cpp4
43 files changed, 214 insertions, 181 deletions
diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h
index eb9168707a..5e730fc12c 100644
--- a/include/llvm/CodeGen/CallingConvLower.h
+++ b/include/llvm/CodeGen/CallingConvLower.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CallingConv.h"
namespace llvm {
class TargetRegisterInfo;
@@ -142,7 +143,7 @@ typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT,
/// return values. It captures which registers are already assigned and which
/// stack slots are used. It provides accessors to allocate these values.
class CCState {
- unsigned CallingConv;
+ CallingConv::ID CallingConv;
bool IsVarArg;
const TargetMachine &TM;
const TargetRegisterInfo &TRI;
@@ -152,7 +153,7 @@ class CCState {
unsigned StackOffset;
SmallVector<uint32_t, 16> UsedRegs;
public:
- CCState(unsigned CC, bool isVarArg, const TargetMachine &TM,
+ CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
SmallVector<CCValAssign, 16> &locs, LLVMContext &C);
void addLoc(const CCValAssign &V) {
@@ -161,7 +162,7 @@ public:
LLVMContext &getContext() const { return Context; }
const TargetMachine &getTarget() const { return TM; }
- unsigned getCallingConv() const { return CallingConv; }
+ CallingConv::ID getCallingConv() const { return CallingConv; }
bool isVarArg() const { return IsVarArg; }
unsigned getNextStackOffset() const { return StackOffset; }
diff --git a/include/llvm/Function.h b/include/llvm/Function.h
index 7ff18b376d..088c99952e 100644
--- a/include/llvm/Function.h
+++ b/include/llvm/Function.h
@@ -19,6 +19,7 @@
#define LLVM_FUNCTION_H
#include "llvm/GlobalValue.h"
+#include "llvm/CallingConv.h"
#include "llvm/BasicBlock.h"
#include "llvm/Argument.h"
#include "llvm/Attributes.h"
@@ -86,7 +87,7 @@ private:
AttrListPtr AttributeList; ///< Parameter attributes
// The Calling Convention is stored in Value::SubclassData.
- /*unsigned CallingConvention;*/
+ /*CallingConv::ID CallingConvention;*/
friend class SymbolTableListTraits<Function, Module>;
@@ -150,12 +151,14 @@ public:
unsigned getIntrinsicID() const;
bool isIntrinsic() const { return getIntrinsicID() != 0; }
- /// getCallingConv()/setCallingConv(uint) - These method get and set the
+ /// getCallingConv()/setCallingConv(CC) - These method get and set the
/// calling convention of this function. The enum values for the known
/// calling conventions are defined in CallingConv.h.
- unsigned getCallingConv() const { return SubclassData >> 1; }
- void setCallingConv(unsigned CC) {
- SubclassData = (SubclassData & 1) | (CC << 1);
+ CallingConv::ID getCallingConv() const {
+ return static_cast<CallingConv::ID>(SubclassData >> 1);
+ }
+ void setCallingConv(CallingConv::ID CC) {
+ SubclassData = (SubclassData & 1) | (static_cast<unsigned>(CC) << 1);
}
/// getAttributes - Return the attribute list for this Function.
diff --git a/include/llvm/Instructions.h b/include/llvm/Instructions.h
index 4460f8890a..e6f1c54483 100644
--- a/include/llvm/Instructions.h
+++ b/include/llvm/Instructions.h
@@ -20,6 +20,7 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Attributes.h"
#include "llvm/BasicBlock.h"
+#include "llvm/CallingConv.h"
#include "llvm/LLVMContext.h"
#include "llvm/ADT/SmallVector.h"
#include <iterator>
@@ -1042,9 +1043,11 @@ public:
/// getCallingConv/setCallingConv - Get or set the calling convention of this
/// function call.
- unsigned getCallingConv() const { return SubclassData >> 1; }
- void setCallingConv(unsigned CC) {
- SubclassData = (SubclassData & 1) | (CC << 1);
+ CallingConv::ID getCallingConv() const {
+ return static_cast<CallingConv::ID>(SubclassData >> 1);
+ }
+ void setCallingConv(CallingConv::ID CC) {
+ SubclassData = (SubclassData & 1) | (static_cast<unsigned>(CC) << 1);
}
/// getAttributes - Return the parameter attributes for this call.
@@ -2382,9 +2385,11 @@ public:
/// getCallingConv/setCallingConv - Get or set the calling convention of this
/// function call.
- unsigned getCallingConv() const { return SubclassData; }
- void setCallingConv(unsigned CC) {
- SubclassData = CC;
+ CallingConv::ID getCallingConv() const {
+ return static_cast<CallingConv::ID>(SubclassData);
+ }
+ void setCallingConv(CallingConv::ID CC) {
+ SubclassData = static_cast<unsigned>(CC);
}
/// getAttributes - Return the parameter attributes for this invoke.
diff --git a/include/llvm/Support/CallSite.h b/include/llvm/Support/CallSite.h
index 0a21060f2d..285b558afc 100644
--- a/include/llvm/Support/CallSite.h
+++ b/include/llvm/Support/CallSite.h
@@ -26,6 +26,7 @@
#include "llvm/Attributes.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/BasicBlock.h"
+#include "llvm/CallingConv.h"
#include "llvm/Instruction.h"
namespace llvm {
@@ -61,8 +62,8 @@ public:
/// getCallingConv/setCallingConv - get or set the calling convention of the
/// call.
- unsigned getCallingConv() const;
- void setCallingConv(unsigned CC);
+ CallingConv::ID getCallingConv() const;
+ void setCallingConv(CallingConv::ID CC);
/// getAttributes/setAttributes - get or set the parameter attributes of
/// the call.
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 00a455c360..a7ae0ef6f8 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -1116,7 +1116,7 @@ public:
///
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -1147,8 +1147,9 @@ public:
std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, bool isInreg, unsigned NumFixedArgs,
- unsigned CallConv, bool isTailCall, bool isReturnValueUsed,
- SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl);
+ CallingConv::ID CallConv, bool isTailCall,
+ bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
+ SelectionDAG &DAG, DebugLoc dl);
/// LowerCall - This hook must be implemented to lower calls into the
/// the specified DAG. The outgoing arguments to the call are described
@@ -1164,7 +1165,7 @@ public:
///
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -1179,7 +1180,7 @@ public:
/// value.
///
virtual SDValue
- LowerReturn(SDValue Chain, unsigned CallConv, bool isVarArg,
+ LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
assert(0 && "Not Implemented");
@@ -1283,7 +1284,7 @@ public:
/// should override this function.
virtual bool
IsEligibleForTailCallOptimization(SDValue Callee,
- unsigned CalleeCC,
+ CallingConv::ID CalleeCC,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp
index 4f7a440c01..9424328910 100644
--- a/lib/AsmParser/LLParser.cpp
+++ b/lib/AsmParser/LLParser.cpp
@@ -998,7 +998,7 @@ bool LLParser::ParseOptionalVisibility(unsigned &Res) {
/// ::= 'arm_aapcs_vfpcc'
/// ::= 'cc' UINT
///
-bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
+bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
switch (Lex.getKind()) {
default: CC = CallingConv::C; return false;
case lltok::kw_ccc: CC = CallingConv::C; break;
@@ -1009,8 +1009,18 @@ bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
case lltok::kw_arm_apcscc: CC = CallingConv::ARM_APCS; break;
case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
- case lltok::kw_cc: Lex.Lex(); return ParseUInt32(CC);
+ case lltok::kw_cc: {
+ unsigned ArbitraryCC;
+ Lex.Lex();
+ if (ParseUInt32(ArbitraryCC)) {
+ return true;
+ } else
+ CC = static_cast<CallingConv::ID>(ArbitraryCC);
+ return false;
+ }
+ break;
}
+
Lex.Lex();
return false;
}
@@ -2357,7 +2367,8 @@ bool LLParser::ParseFunctionHeader(Function *&Fn, bool isDefine) {
LocTy LinkageLoc = Lex.getLoc();
unsigned Linkage;
- unsigned Visibility, CC, RetAttrs;
+ unsigned Visibility, RetAttrs;
+ CallingConv::ID CC;
PATypeHolder RetType(Type::getVoidTy(Context));
LocTy RetTypeLoc = Lex.getLoc();
if (ParseOptionalLinkage(Linkage) ||
@@ -2917,7 +2928,8 @@ bool LLParser::ParseSwitch(Instruction *&Inst, PerFunctionState &PFS) {
/// OptionalAttrs 'to' TypeAndValue 'unwind' TypeAndValue
bool LLParser::ParseInvoke(Instruction *&Inst, PerFunctionState &PFS) {
LocTy CallLoc = Lex.getLoc();
- unsigned CC, RetAttrs, FnAttrs;
+ unsigned RetAttrs, FnAttrs;
+ CallingConv::ID CC;
PATypeHolder RetType(Type::getVoidTy(Context));
LocTy RetTypeLoc;
ValID CalleeID;
@@ -3265,7 +3277,8 @@ bool LLParser::ParsePHI(Instruction *&Inst, PerFunctionState &PFS) {
/// ParameterList OptionalAttrs
bool LLParser::ParseCall(Instruction *&Inst, PerFunctionState &PFS,
bool isTail) {
- unsigned CC, RetAttrs, FnAttrs;
+ unsigned RetAttrs, FnAttrs;
+ CallingConv::ID CC;
PATypeHolder RetType(Type::getVoidTy(Context));
LocTy RetTypeLoc;
ValID CalleeID;
diff --git a/lib/AsmParser/LLParser.h b/lib/AsmParser/LLParser.h
index 4bdbbfeab2..545be465f2 100644
--- a/lib/AsmParser/LLParser.h
+++ b/lib/AsmParser/LLParser.h
@@ -126,7 +126,7 @@ namespace llvm {
bool HasLinkage; return ParseOptionalLinkage(Linkage, HasLinkage);
}
bool ParseOptionalVisibility(unsigned &Visibility);
- bool ParseOptionalCallingConv(unsigned &CC);
+ bool ParseOptionalCallingConv(CallingConv::ID &CC);
bool ParseOptionalAlignment(unsigned &Alignment);
bool ParseOptionalCommaAlignment(unsigned &Alignment);
bool ParseIndexList(SmallVectorImpl<unsigned> &Indices);
diff --git a/lib/Bitcode/Reader/BitcodeReader.cpp b/lib/Bitcode/Reader/BitcodeReader.cpp
index f9cfe91625..e0b5fd90c2 100644
--- a/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -1417,7 +1417,7 @@ bool BitcodeReader::ParseModule(const std::string &ModuleID) {
Function *Func = Function::Create(FTy, GlobalValue::ExternalLinkage,
"", TheModule);
- Func->setCallingConv(Record[1]);
+ Func->setCallingConv(static_cast<CallingConv::ID>(Record[1]));
bool isProto = Record[2];
Func->setLinkage(GetDecodedLinkage(Record[3]));
Func->setAttributes(getAttributes(Record[4]));
@@ -1918,7 +1918,8 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
I = InvokeInst::Create(Callee, NormalBB, UnwindBB,
Ops.begin(), Ops.end());
- cast<InvokeInst>(I)->setCallingConv(CCInfo);
+ cast<InvokeInst>(I)->setCallingConv(
+ static_cast<CallingConv::ID>(CCInfo));
cast<InvokeInst>(I)->setAttributes(PAL);
break;
}
@@ -2056,7 +2057,8 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
}
I = CallInst::Create(Callee, Args.begin(), Args.end());
- cast<CallInst>(I)->setCallingConv(CCInfo>>1);
+ cast<CallInst>(I)->setCallingConv(
+ static_cast<CallingConv::ID>(CCInfo>>1));
cast<CallInst>(I)->setTailCall(CCInfo & 1);
cast<CallInst>(I)->setAttributes(PAL);
break;
diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index 60c3056902..fbe40b6786 100644
--- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -20,7 +20,7 @@
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
-CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
+CCState::CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm,
SmallVector<CCValAssign, 16> &locs, LLVMContext &C)
: CallingConv(CC), IsVarArg(isVarArg), TM(tm),
TRI(*TM.getRegisterInfo()), Locs(locs), Context(C) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 0a161d0dca..555ef9e1b0 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -989,7 +989,8 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
}
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
- unsigned CallConv = DAG.getMachineFunction().getFunction()->getCallingConv();
+ CallingConv::ID CallConv =
+ DAG.getMachineFunction().getFunction()->getCallingConv();
Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
Outs, getCurDebugLoc(), DAG);
@@ -5613,7 +5614,7 @@ std::pair<SDValue, SDValue>
TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned NumFixedArgs,
- unsigned CallConv, bool isTailCall,
+ CallingConv::ID CallConv, bool isTailCall,
bool isReturnValueUsed,
SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 8d79e5b731..1ade8f8926 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -685,7 +685,7 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
/// given CallingConvention value.
-CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
+CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
bool Return,
bool isVarArg) const {
switch (CC) {
@@ -715,7 +715,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
/// appropriate copies out of appropriate physical registers.
SDValue
ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -846,7 +846,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
/// nodes.
SDValue
ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -1050,7 +1050,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
SDValue
ARMTargetLowering::LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
@@ -1550,7 +1550,7 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue
ARMTargetLowering::LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 80d1f00f94..3ec76cfbfc 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -246,7 +246,7 @@ namespace llvm {
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
- CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return, bool isVarArg) const;
+ CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA,
@@ -273,21 +273,21 @@ namespace llvm {
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -296,7 +296,7 @@ namespace llvm {
virtual SDValue
LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
};
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 42f269d9cc..ac6be655e5 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -232,7 +232,7 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
SDValue
AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -348,7 +348,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
///
SDValue
AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) {
@@ -390,7 +390,7 @@ AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
SDValue
AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -471,7 +471,7 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
SDValue
AlphaTargetLowering::LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index fd011242b2..90e5d1f0dd 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -82,7 +82,7 @@ namespace llvm {
const char *getTargetNodeName(unsigned Opcode) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
@@ -108,14 +108,14 @@ namespace llvm {
virtual SDValue
LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg, bool isTailCall,
+ CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -123,7 +123,7 @@ namespace llvm {
virtual SDValue
LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
};
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp
index 1ca1fae9df..7c36b01b16 100644
--- a/lib/Target/Blackfin/BlackfinISelLowering.cpp
+++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp
@@ -161,7 +161,7 @@ SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
SDValue
BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
@@ -218,7 +218,7 @@ BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
SDValue
BlackfinTargetLowering::LowerReturn(SDValue Chain,
- unsigned CallConv, bool isVarArg,
+ CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) {
@@ -275,7 +275,7 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain,
SDValue
BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
- unsigned CallConv, bool isVarArg,
+