diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-09 05:36:17 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-09 05:36:17 +0000 |
| commit | 65a419a1045972729f91f82a378b7f4b7f6a2be5 (patch) | |
| tree | 638a89da812d5084ed4fb95f6256ee5c9cf63f2e | |
| parent | 0cb34c471448b134acfa87076d08f832e493f4fe (diff) | |
Disable formation of rlwinm instructions from SRA bases. This fixes
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23670 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index d0059bbcd3..09f980be4e 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -217,7 +217,7 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { return false; } -// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate +// isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate // and mask opcode and mask operation. static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, unsigned &SH, unsigned &MB, unsigned &ME) { @@ -1278,7 +1278,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) { } case ISD::SRA: { unsigned Imm, SH, MB, ME; - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && + if (0 &&isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && isRotateAndMask(N, Imm, true, SH, MB, ME)) CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0).getOperand(0)), |