diff options
author | Chris Lattner <sabre@nondot.org> | 2005-10-15 21:40:12 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2005-10-15 21:40:12 +0000 |
commit | 651dea74f6a362d30bc61fd0b549da7707af5bf8 (patch) | |
tree | dccbe0708740d3ed5667ba2973409b366cbfc327 | |
parent | 7e82f1322c2ddadf5e92b6439f97276d17cba166 (diff) |
remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23749 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 8396da66db..48e6a21c76 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -233,7 +233,7 @@ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, if (IsShiftMask) Mask = Mask << Shift; // determine which bits are made indeterminant by shift Indeterminant = ~(0xFFFFFFFFu << Shift); - } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { + } else if (Opcode == ISD::SRL) { // apply shift right to mask if it comes first if (IsShiftMask) Mask = Mask >> Shift; // determine which bits are made indeterminant by shift @@ -1277,13 +1277,8 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) { return SDOperand(N, 0); } case ISD::SRA: { - unsigned Imm, SH, MB, ME; - if (0 &&isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && - isRotateAndMask(N, Imm, true, SH, MB, ME)) - CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, - Select(N->getOperand(0).getOperand(0)), - getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); - else if (isIntImmediate(N->getOperand(1), Imm)) + unsigned Imm; + if (isIntImmediate(N->getOperand(1), Imm)) CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)), getI32Imm(Imm)); else |