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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-08-11 17:05:47 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-08-11 17:05:47 +0000 |
| commit | 6236f7f2b66cecdfe18c7c9b77b59cb922617f3f (patch) | |
| tree | 33dba6a80cf03308416423a4a483099bb3d90bfe | |
| parent | f80a894bf03ea65624a25b8f64bfcc9c6cf7f80f (diff) | |
Add a comment, per Bruno's CR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137313 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 94faae5b55..666ce3c07e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -12593,6 +12593,9 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI = DAG.getTargetLoweringInfo(); // If we are saving a concatination of two XMM registers, perform two stores. + // This is better in Sandy Bridge cause one 256-bit mem op is done via two + // 128-bit ones. If in the future the cost becomes only one memory access the + // first version would be better. if (VT.getSizeInBits() == 256 && StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && StoredVal.getNumOperands() == 2) { |