diff options
| author | Andrew Trick <atrick@apple.com> | 2011-01-04 00:32:57 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-01-04 00:32:57 +0000 |
| commit | 6018deefe823598a3bbe03de9af354d269ae2130 (patch) | |
| tree | 1514eb254ea72aa977b4f62e8cfacaf020c21c5c | |
| parent | a1cb585384f593517a9b8f48693f5e478b833fba (diff) | |
Fix the ARM IIC_iCMPsi itinerary and add an important assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index eab6b98a84..a9632be61f 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -123,7 +123,8 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1], [A9_LdBypass, A9_LdBypass]>, - InstrItinData<IIC_iCMPsi , [InstrStage<2, [A9_ALU0, A9_ALU1]>], + InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1], [A9_LdBypass, NoBypass]>, InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<3, [A9_ALU0, A9_ALU1]>], diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 6290e67675..2b53cfd973 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -240,6 +240,7 @@ void ARMSubtarget::computeIssueWidth() { // clear the lowest bit allStage1Units ^= allStage1Units & ~(allStage1Units - 1); } + assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); } bool ARMSubtarget::enablePostRAScheduler( |