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authorDuncan Sands <baldrick@free.fr>2012-04-30 11:56:58 +0000
committerDuncan Sands <baldrick@free.fr>2012-04-30 11:56:58 +0000
commit5ff30e70f8dc4ddfdb3bd6925ccdf524130a7b95 (patch)
treef063cefea11403837e9ffc79cad33e8d7cbf9d14
parentbfbab99b58aa530d5d6aa886ef66be42a047c756 (diff)
Just mark the sign bit as known zero, rather than any other irrelevant bits
known zero in the LHS. Fixes PR12541. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155818 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Analysis/ValueTracking.cpp2
-rw-r--r--test/Transforms/InstCombine/2012-04-30-SRem.ll12
2 files changed, 13 insertions, 1 deletions
diff --git a/lib/Analysis/ValueTracking.cpp b/lib/Analysis/ValueTracking.cpp
index a430f6281e..1418e01d7c 100644
--- a/lib/Analysis/ValueTracking.cpp
+++ b/lib/Analysis/ValueTracking.cpp
@@ -564,7 +564,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
Depth+1);
// If it's known zero, our sign bit is also zero.
if (LHSKnownZero.isNegative())
- KnownZero |= LHSKnownZero;
+ KnownZero.setBit(BitWidth - 1);
}
break;
diff --git a/test/Transforms/InstCombine/2012-04-30-SRem.ll b/test/Transforms/InstCombine/2012-04-30-SRem.ll
new file mode 100644
index 0000000000..a285d5aea5
--- /dev/null
+++ b/test/Transforms/InstCombine/2012-04-30-SRem.ll
@@ -0,0 +1,12 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+; PR12541
+
+define i32 @foo(i32 %x) {
+ %y = xor i32 %x, 3
+ %z = srem i32 1656690544, %y
+ %sext = shl i32 %z, 24
+ %s = ashr exact i32 %sext, 24
+ ret i32 %s
+; CHECK-NOT: and
+; The shifts were wrongly being turned into an and with 112
+}