diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-02 20:24:25 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-02 20:24:25 +0000 |
| commit | 5f450d2948ac5bd83a31fbfff89e17b0e2536a80 (patch) | |
| tree | c29754e8e130e5c18ca2832c8968577a47dbaf66 | |
| parent | a3a68bde2103e04d30b80b3d18030867bf78ea7b (diff) | |
add more condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30056 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARM.h | 30 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/branch.ll | 36 |
3 files changed, 63 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 62f2a0d2ee..7e49ae2118 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -23,16 +23,42 @@ namespace llvm { // Enums corresponding to ARM condition codes namespace ARMCC { enum CondCodes { + EQ, NE, - EQ + CS, + CC, + MI, + PL, + VS, + VC, + HI, + LS, + GE, + LT, + GT, + LE, + AL }; } static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { switch (CC) { default: assert(0 && "Unknown condition code"); - case ARMCC::NE: return "ne"; case ARMCC::EQ: return "eq"; + case ARMCC::NE: return "ne"; + case ARMCC::CS: return "cs"; + case ARMCC::CC: return "cc"; + case ARMCC::MI: return "mi"; + case ARMCC::PL: return "pl"; + case ARMCC::VS: return "vs"; + case ARMCC::VC: return "vc"; + case ARMCC::HI: return "hi"; + case ARMCC::LS: return "ls"; + case ARMCC::GE: return "ge"; + case ARMCC::LT: return "lt"; + case ARMCC::GT: return "gt"; + case ARMCC::LE: return "le"; + case ARMCC::AL: return "al"; } } diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 9dd14618dc..34b04ffd21 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -89,6 +89,8 @@ static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) { default: assert(0 && "Unknown condition code!"); case ISD::SETNE: return ARMCC::NE; case ISD::SETEQ: return ARMCC::EQ; + case ISD::SETGE: return ARMCC::GE; + case ISD::SETUGE: return ARMCC::CS; } } diff --git a/test/CodeGen/ARM/branch.ll b/test/CodeGen/ARM/branch.ll index 21e43127c3..e4ac1af4ce 100644 --- a/test/CodeGen/ARM/branch.ll +++ b/test/CodeGen/ARM/branch.ll @@ -1,7 +1,37 @@ -; RUN: llvm-as < %s | llc -march=arm -void %f(int %a, int* %v) { +; RUN: llvm-as < %s | llc -march=arm && +; RUN: llvm-as < %s | llc -march=arm | grep bne && +; RUN: llvm-as < %s | llc -march=arm | grep bge && +; RUN: llvm-as < %s | llc -march=arm | grep bcs + +void %f1(int %a, int %b, int* %v) { +entry: + %tmp = seteq int %a, %b ; <bool> [#uses=1] + br bool %tmp, label %cond_true, label %return + +cond_true: ; preds = %entry + store int 0, int* %v + ret void + +return: ; preds = %entry + ret void +} + +void %f2(int %a, int %b, int* %v) { +entry: + %tmp = setlt int %a, %b ; <bool> [#uses=1] + br bool %tmp, label %cond_true, label %return + +cond_true: ; preds = %entry + store int 0, int* %v + ret void + +return: ; preds = %entry + ret void +} + +void %f3(uint %a, uint %b, int* %v) { entry: - %tmp = seteq int %a, 0 ; <bool> [#uses=1] + %tmp = setlt uint %a, %b ; <bool> [#uses=1] br bool %tmp, label %cond_true, label %return cond_true: ; preds = %entry |