diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-01 19:14:02 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-01 19:14:02 +0000 |
| commit | 5d5b17bf9140f02ca1420731e7b1c1d3ad1d9f02 (patch) | |
| tree | 7c740ec9647f92042640e980a70e4dc44352edb4 | |
| parent | cf8bf388ea2169c5458f31a69c76c80c0ab467bf (diff) | |
simplify call code, remove pseudo ops for div and rem, track more loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22323 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.td | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index 4254680fd9..e6957ab692 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -45,23 +45,6 @@ let Defs = [R29] in let Uses = [R27] in def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">; -//RESULTS of these go to R27 -//These are also evil as the assembler expands them into calls -let Uses = [R29], - Defs = [R28, R23, R24, R25, R27] in -{ - def REMQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$$27">; //unsigned remander - def REMQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$$27">; //signed remander - def DIVQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$$27">; //unsigned division - def DIVQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$$27">; //signed division -} - -//This is an improvement on the old style setcc (FP) -//def CC2INT_INV : PseudoInstAlpha<(ops GPRC:$RES, FPRC:$COND), -// "lda $RES,1($$31)\n\tfbeq $COND, 42f\n\tbis $$31,$$31,$RES\n42:\n">; -//def CC2INT : PseudoInstAlpha<(ops GPRC:$RES, FPRC:$COND), -// "lda $RES,1($$31)\n\tfbne $COND, 42f\n\tbis $$31,$$31,$RES\n42:\n">; - //An even better improvement on the Int = SetCC(FP): SelectCC! //These are evil because they hide control flow in a MBB //really the ISel should emit multiple MBB |